• 제목/요약/키워드: Chemical Mechanical Polishing (CMP)

검색결과 428건 처리시간 0.026초

$Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) 박막의 CMP 메커니즘 연구 (A Study on CMP Mechanism of $Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) Thin Films)

  • 신상헌;고필주;김남훈;이우선
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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    • pp.1450-1451
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    • 2006

  • In this paper, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) ferroelectric fan was fabricated by the sol-gel method. Removal rate and non-uniformity (WIWNU%) were examined by change of silica slurries pH(10.3, 11.3, 12.3). Surface roughness of BLT thin films before and after CMP process was inquired into by atomic force microscopy (AFM). Effects of silica slurries pH(10.3, 11.3, 12.3) were investigated on the CMP performance of BLT film by the surface analysis of X-ray photoelectron spectroscopy(XPS).

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STI CMP후 Topology에 따른 Gate Etch, Transistor 특성 변화 (Property variation of transistor in Gate Etch Process versus topology of STI CMP)

  • 김상용;정헌상;박민우;김창일;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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    • pp.181-184
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    • 2001

  • Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

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STI CMP후 Topology에 따른 Gate Etch, Transistor 특성 변화 (Property variation of transistor in Gate Etch Process versus topology of STI CMP)

  • 김상용;정헌상;박민우;김창일;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집
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    • pp.181-184
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    • 2001

  • Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

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광역평탄화에 따른 투명전도박막의 표면특성 (Surface Properties of ITO Thin Film by Planarization)

  • 최권우;이우선;서용진
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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    • pp.95-96
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    • 2006

  • ITO thin film is generally fabricated by various methods such as spray, CVD, evaporation, electron gun deposition, direct current electroplating, high frequency sputtering, and reactive DC sputtering. However, some problems such as peaks, bumps, large particles, and pin-holes on the surface of ITO thin film were reported, which caused the destruction of color quality, the reduction of device life time, and short-circuit. Chemical mechanical polishing (CMP) process is one of the suitable solutions which could solve the problems.

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기계.화학적인 연마에서 슬러리의 특성에 따른 나노토포그래피의 영향과 numerical시뮬레이션 (Effect of Slurry Characteristics on Nanotopography Impact in Chemical Mechanical Polishing and Its Numerical Simulation)

  • Takeo Katoh;Kim, Min-Seok;Ungyu Paik;Park, Jea-Gun
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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    • pp.63-63
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    • 2003

  • The nanotopography of silicon wafers has emerged as an important factor in the STI process since it affects the post-CMP thickness deviation (OTD) of dielectric films. Ceria slurry with surfactant is widely applied to STI-CMP as it offers high oxide-to-nitride removal selectivity. Aiming to control the nanotopography impact through ceria slurry characteristics, we examhed the effect of surfactant concentration and abrasive size on the nanotopography impact. The ceria slurries for this study were produced with cerium carbonate as the starting material. Four kinds of slurry with different size of abrasives were prepared through a mechanical treatment The averaged abrasive size for each slurry varied from 70 nm to 290 nm. An anionic organic surfactant was added with the concentration from 0 to 0.8 wt %. We prepared commercial 8 inch silicon wafers. Oxide Shu were deposited using the plasma-enhanced tetra-ethyl-ortho-silicate (PETEOS) method, The films on wafers were polished on a Strasbaugh 6EC. Film thickness before and after CMP was measured with a spectroscopic ellipsometer, ES4G (SOPRA). The nanotopogrphy height of the wafer was measured with an optical interferometer, NanoMapper (ADE Phase Shift)

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