• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.369-372
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• 2002

To remedy both the degradation and saturation of the output voltages in the modified Dickson pump, a new multistage charge pump circuit is presented in this paper. Here using PMOS charge-transfer switches instead of NMOS ones eliminates the necessity of diode-configured output stage in the modified-Dickson pump, achieving the improved voltage pumping gain and its output voltages proportional to the stage numbers. Measurement indicates that VOUT/3VDD of this new pump circuit with two stages reaches to a value as high as 0.94V even with low VDD=1.0 V, strongly addressing that this scheme is very favorable at low-voltage memory applications.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.845-848
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• 2005

This paper describes a 4.224GHz CMOS charge pump PLL for Mode 1 MB-OFDM UWB hopping carrier generation. It includes a qudrature VCO of which the frequency range is from 3.98GHz to 4.47GHz(@ 0.4 to 1.5 V), a divider, a PFD, a loop filter, a charge pump, and a lock detector. Designed in a 0.18um CMOS technology, the PLL draws 6.6mA from a 1.8V supply. The phase noise of the designed VCO is -133dBc/Hz@3MHz.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.1011-1014
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• 2004

In this paper, we present a new DC-DC converter for gate driver circuit in low temperature poly-Si TFT technology. It is composed of a newly developed charge pump circuit and a regulator circuit. When the input voltage is 5V, the efficiency of a positive charge pump used in the DC-DC converter and that of a negative charge pump is 69.0% and 57.1%, respectively. The output voltage of DC-DC converter varies 200mV when the target voltages of DC-DC converter are 9V, -6V and the threshold voltage of TFTs varies ${\pm}$ 0.5V.

• Journal of Power Electronics
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• 제16권4호
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• pp.1277-1287
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• 2016

This study proposes a novel isolated high step-up galvanic converter, which is suitable for renewable energy applications and integrates a boost converter, a coupled inductor, a charge pump capacitor cell, and an LC snubber. The proposed converter comprises an input inductor and thus features a continuous input current, which extends the life of the renewable energy chip. Furthermore, the proposed converter can achieve a high voltage gain without an extremely large duty cycle and turn ratio of the coupled inductor by using the charge pump capacitor cell. The leakage inductance energy can be recycled to the output capacitor of the boost converter via the LC snubber and then transferred to the output load. As a result, the voltage spike can be suppressed to a low voltage level. Finally, the basic operating principles and experimental results are provided to verify the effectiveness of the proposed converter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.214-215
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• 2011

일반적으로 멀티레벨 인버터는 고조파 저감을 위하여 출력전압의 레벨 수에 비례하는 다수의 플로팅(floating)된 입력 전압원 또는 다수의 절연 변압기를 필요로 하므로 시스템이 복잡하고 가격이 높은 단점을 갖는다. 이를 위해 본 논문에서는 단 한 개의 입력 전압원 만으로 원하는 만큼의 출력전압 레벨 수를 획득할 수 있는 Charge Pump 방식의 멀티레벨 인버터를 제안한다. 제안된 인버터는 시스템 구성이 매우 간단하여 제작단가 및 전력변환 효율을 개선시킬 수 있는 장점을 가진다. 최종적으로 제안 인버터의 특성에 대한 이론적 분석과 모의실험을 통해 그 우수성을 검증한다.

• Journal of Information Display
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• 제7권1호
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• pp.35-40
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• 2006

Organic light-emitting diode (OLED) display panel using the charge-pump (CP) pixel addressing scheme was fabricated, and the results show that it is applicable for information display. A CP-OLED panel with 64 ${\times}$ 64 pixels consisting of thin-film capacitors and amorphous silicon Schottky diodes was fabricated using conventional thin-film processes. The pixel drive circuit passes electrical current into the OLED cell during most of the frame period as in the thin-film transistor (TFT)-based active-matrix (AM) OLED displays. In this study, the panel was operated at a voltage level of below 4 V, and this operation voltage can be reduced by eliminating the overlap capacitance between the column bus line and the common electrode.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.394-397
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• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.375-377
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• 2007

본 논문에서는 LCD backlight 구동을 위한 Dual charge pump inverter를 제안하였다. 제안 회로는 넓은 입력 및 부하 범위에서 영전압 스위칭(Zero Voltage Switching) 동작을 보장하여 효율이 높은 장점을 가진다. 기존 full bridge 방식의 회로와 비교하여 동등한 수준의 소자 전압 스트레스를 가지며, 트랜스포머 1차측 양단 전압을 Full_Bridge 방식에 비해 2배로 만들 수 있어 트랜스포머의 턴비 감소 효과를 얻을 수 있다. 또한 각 소자 전류 스트레스를 기존 대비 1/2로 줄일 수 있는 장점을 가진다. 위와 같이 제안한 회로의 타당성 검증을 위해 시뮬레이션과 40인치 LCD Pannel에 적용하여 실험을 수행하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.265-267
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• 2007

본 논문은 LCD Backlight 구동을 위한 새로운 방식의 회로를 제안한다. 제안된 회로는 Charge Pump 캐패시터를 이용한 Half-Bridge 타입의 인버터로 Full Bridge 회로와 동등한 성능을 갖는다. 제안 회로는 넓은 입력 범위와 넓은 부하 범위에서 영전압 스위칭(ZVS) 확보가 가능해서 인버터의 고효율 동작이 확보되고, MOSFET의 surge 및 noise를 저감시킨다. 제안된 회로의 동작 원리를 설명하고, 시뮬레이션 및 40" LCD 패널에 실제 적용 실험하여, 회로의 동작을 입증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.473-476
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• 2004

AS supply voltage of DRAM is scaled down, voltage circuit that is stable from external noise is more important. $V_{PP}$ voltage is very important, it is biased to gate of memory cell transistor and possible to read and write without voltage down. It has both high pump gain and high power efficiency therefore charge pump circuit is proposed. The circuit is simulated by 0.18${\mu}m$ memory process and 1.2V supply voltage. Compare to CCTS, it is improved 0.43V of pump gain, $3.06\%$ of power efficiency at 6 stage.