• 태양에너지
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• 제19권3호
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• pp.63-73
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• 1999

Ice storage systems are used to shift the peak load in day time into night time in summer. This paper describes a system simulation of partial ice storage system composed of an encapsulated ice storage tank, a screw compressor chiller, a heat exchanger, and a brine pump. For the system simulation, a one-dimensional model of ice storage tank is developed and validated by comparison with the performance data from measurements of an ice storage tank installed at a building. The control strategies considered in this study are chiller priority and storage priority being used commercially. The system is simulated with design cooling load of 600 RT peak load in design day and with off-design day cooling load, and the electric energy costs of the two control strategies for the same system size are compared. As a result of calculation, the energy consumption in a week for storage priority is higher than that for chiller priority control. However due to lower cost of night electric charge rate, energy cost for storage priority control is lower than chiller priority.

• ETRI Journal
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• 제37권6호
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.499-500
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• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.48-57
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• 2013

This paper presents a power management system of the dye-sensitized solar cell (DSSC) for ubiquitous sensor network (USN) applications. The charge pump with a luminance-controlled oscillator regulates the load impedance of the DSSC to track the maximum power point (MPP) under various light intensities. The low drop-out regulator with a hysteresis comparator supplies intermittent power pulses that are wide enough for USN to communicate with a host transponder even under dim light conditions. With MPP tracking, approximately 50% more power is harvested over a wide range of light intensity. The power management system fabricated using $0.13{\mu}m$ CMOS technology works with DSSC to provide power pulses of $36{\mu}A$. The duration of pulses is almost constant around $80{\mu}s$ (6.5 nJ/pulse), while the pulse spacing is inversely proportional to the light intensity.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.379-382
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• 2013

기존의 빛 에너지 하베스팅 회로에서는 MPPT(Maximum Power Point Tracking) 기능을 구현하기 위해 전력변환기(power converter)를 동작시키기 위한 클럭의 주파수나 듀티 싸이클(duty cycle)을 지속적으로 변화시키는 방법을 사용하고 있다. 본 논문에서는 전력변환기에 전력 공급을 위한 스위치의 듀티 싸이클을 제어하여 MPPT 기능을 구현하는 새로운 방법을 제안하였다. 제안된 회로는 0.35um CMOS 공정으로 설계 되었으며 칩 면적은 패드를 포함하여 $770um{\times}800um$이다.

• ETRI Journal
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• 제33권5호
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• pp.752-758
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• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.425-428
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• 2011

본 논문에서는 간단한 Maximum Power Point Tracking이 적용된 micro-scale의 빛에너지 하베스팅 회로를 제안한다. 에너지 변환기로는 온칩 PV cell 대신 이와 비슷한 출력을 하는 초소형 PV cell을 사용하였다. 적용된 MPPT는 PV cell의 개방전압($V_{OC}$)와 MPP전압($V_{MPP}$)과의 관계를 이용하였고 이는 pilot PV cell을 이용함으로써 가능하였다. 설계결과 MPPT control을 적용했을 때 부하가 큰 경우에도 대략 $V_{MPP}$ 전압을 부하에 공급함으로써 부하에 연결된 회로가 정상적으로 동작하는 것을 확인하였다. 제안된 회로는 TSMC 0.18um CMOS 공정으로 설계되었다.

• Transactions on Electrical and Electronic Materials
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• 제11권1호
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• 한국지하수토양환경학회지:지하수토양환경
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• 제20권2호
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• pp.41-46
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• 2015

The drag of the excess charge in an electrical double layer at the solid fluid interface due to water flow induces the streaming current, i.e., the streaming potential (SP). Here we introduce a sandbox experiment to study this hydroelectric coupling in case of a tracer test. An acrylic tank was filled up with homogeneous sand as a sand aquifer, and the upstream and downstream reservoirs were connected to the sand aquifer to control the hydraulic gradient. Under a steady-state water flow condition, a tracer test was performed in the sandbox with the help of peristaltic pump, and tracer samples were collected from the same interval of five screened wells in the sandbox. During the tracer test, SP signals resulting from the distribution of 20 nonpolarizable electrodes were measured at the top of the tank by a multichannel meter. The results showed that there were changes in the observed SP after injection of tracer, which indicated that the SP was likely to be related to the solute transport.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.1188-1191
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• 2003

In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.