• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.107-108
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• 2007

In order to investigate the electrical properties of Hf-silicate as a function of annealing temperature, Hf-silicate deposited by atomic layer deposition (ALD) was studied. After Hf-silicate film deposition, annealing was proceeded at $500^{\circ}C\;and\;700^{\circ}C$. The hysteresis of C-V curves and trapping charge densities were decreased after annealing process. As annealing temperature became higher from $500^{\circ}C\;to\;700^{\circ}C$, the capacitance equivalent thickness (CET) was increased from 1.66 nm to 1.76 nm and the leakage current at -1 V was decreased from $1.70{\times}10^{-4}\;to\;5.68{\times}10^{-5}\;A/cm^2$.

• Bulletin of the Korean Chemical Society
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• v.14 no.6
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• pp.740-743
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• 1993

By considering both electron-electron and electron-lattice interactions, the effect of charge transfer on the bond structure and electronic states of $C_{60}$ is studied without configuration limitation. The results show that the electron-electron interaction does not eliminate the layer structure of the bond distortion and the self-trapping of transferred electrons. For charged ${C_{60}}^{2-}$, there exist two localized electronic states, which possess laminar wave functions, and four nonequivalent groups of carbon atoms, which induce a fine-structure in the NMR spectrum line.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.60-64
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• 2024

The threshold voltage shift in thin-film transistors (TFTs) is modeled using stretched-exponential (SE) and stretched-hyperbola (SH) functions. These models are derived by introducing empirical parameters into reaction rate equations that describe defect generation or charge trapping caused by hydrogen diffusion in the dielectric or interface. Separately, the dielectric relaxation phenomena are also described by the same reaction rate equations based on defect diffusion. Dielectric relaxation was initially modeled using the SE model, and various models have been proposed using fractional calculus. In this study, the characteristics of the threshold voltage shift and the dielectric relaxation phenomena are compared and analyzed to explore the applicability of analytical models used in the field of dielectric relaxation, in addition to the conventional SE and SH models.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.21-29
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• 2004

Hot carrier degradation characteristics of Nano-scale CMOSFETs with dual gate oxide have been analyzed in depth. It is shown that, PMOSFET lifetime dominate the device lifetime than NMOSFET In Nano-scale CMOSFETs, that is, PMOSFET lifetime under CHC (Channel Hot Carrier) stress is much lower than NMOSFET lifetime under DAHC (Dram Avalanche Hot Carrier) stress. (In case of thin MOSFET, CHC stress showed severe degradation than DAHC for PMOSFET and DAHC than CHC for NMOSFET as well known.) Therefore, the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor in upcoming Nano-scale CMOSFET technology. In case of PMOSFETs, CHC shows enhanced degradation than DAHC regardless of thin and thick PMOSFETs. However, what is important is that hot hole injection rather than hot electron injection play a important role in PMOSFET degradation i.e. threshold voltage increases and saturation drain current decreases due to the hot carrier stresses for both thin and thick PMOSFET. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method. Therefore, suppression of PMOSFET hot carrier degradation or hot hole injection is highly necessary to enhance overall device lifetime or circuit lifetime in Nano-scale CMOSFET technology

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.156-160
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• 2006

Capacitance versus voltage (C-V) curves of Ge-nanocrystal (NC)-embedded MOS capacitors with and without a single capping Al2O3 layer are characterized in this work. C-V curves of the Ge-NC-embedded MOS capacitor with the A12O3 layer are counterclockwise in the voltage sweeps, which indicates tile presence of charge storages in the Ge NCs by the tunnelling of charge carriers between the Si substrate and the Ge NCs. In the Ge-NC-embedded MOS capacitor without Al2O3 layer, clockwise hysteresis of the C-V curves and leftward shifts of the flat band voltages are observed for the embedded MOS capacitor without the Al2O3 layer. It is suggested that the characteristics of the C-V curves are due to the charge trapping at oxygen vacancies within a SiO2 layer. In addition, the illumination of the white light enhances the lower capacitance part of the C-V hysteresis. The origin for the enhancement is discussed in this paper.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.125-131
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• 1991

Boron penetration phenomenon of $p^{+}$ silicon gate with as-deposited amorphous or polycrystalline Si upon high temperature annealing was investigated using high frequency C-V (Capacitance-Volt-age) analysis, CCST(Constant Current Stress Test), TEM(Transmission Electron Microscopy) and SIMS(Secondary Ion Mass Spectroscopy), C-V analysis showed that an as-deposited amorphous Si gate resulted in smaller positive shifts in flatband voltage compared wish a polycrystalline Si gate, thus giving 60-80 percent higher charge-to-breakdown of gate oxides. The reduced boron penetration of amorphous Si gate may be attributed to the fewer grain boundaries available for boron diffusion into the gate oxide and the shallower projected range of $BF_2$ implantation. The relation between electron trapping rate and flatband voltage shift was also discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.1-8
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• 2004

Experimental results are presented for gate oxide degradation, such as SILC and soft breakdown, and its effect on device parameters under negative and positive bias stress conditions using n-MOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both interface and oxide bulk traps are found to dominate the reliability of gate oxide. However, for positive gate voltage, the degradation becomes dominated mainly by interface trap. It was also found the trap generation in the gate oxide film is related to the breakage of Si-H bonds through the deuterium anneal and additional hydrogen anneal experiments. Statistical parameter variations as well as the “OFF” leakage current depend on both electron- and hole-trapping. Our results therefore show that Si or O bond breakage by tunneling electron and hole can be another origin of the investigated gate oxide degradation. This plausible physical explanation is based on both Anode-Hole Injection and Hydrogen-Released model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.939-943
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• 2011

In this paper, reliability of the two sandwiched MIM capacitors of $Al_2O_3-HfO_2-Al_2O_3$ (AHA) and $SiO_2-HfO_2-SiO_2$ (SHS) with hafnium-based dielectrics was analyzed using two kinds of voltage stress; DC and AC voltage stresses. Two MIM capacitors have high capacitance density (8.1 fF/${\mu}m^2$ and 5.2 fF/${\mu}m^2$) over the entire frequency range and low leakage current density of ~1 nA/$cm^2$ at room temperature and 1 V. The charge trapping in the dielectric shows that the relative variation of capacitance (${\Delta}C/C_0$) increases and the variation of voltage linearity (${\alpha}$/${\alpha}_0$) gradually decreases with stress-time under two types of voltage stress. It is also shown that DC voltage stress induced greater variation of capacitance density and voltage linearity than AC voltage stress.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.71-71
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• 2011

Dye-sensitized solar cells (DSCs) have drawn great academic attention due to their potential as low-cost renewable energy sources. DSCs contain a nanostructured TiO2 photoanode, which is a key-component for high conversion efficiency. Particularly, one-dimensional (1-D) nanostructured photoanodes can enhance the electron transport for the efficient collection to the conducting substrate in competition with the recombination processes. This is because photoelectron colletion is determined by trapping/detrapping events along the site of the electron traps (defects, surface states, grain boundaries, and self-trapping). Therefore, 1-D nanostructured photoanodes are advantageous for the fast electron transport due to their desirable features of greatly reduced intercrystalline contacts with specified directionality. In particular, anodic TiO2 nanotube (NT) electrodes recently have been intensively explored owing to their ideal structure for application in DSCs. Besides the enhanced electron transport properties resulted from the 1-D structure, highly ordered and vertically oriented nanostructure of anodic TiO2 NT can contribute additional merits, such as enhanced electrolyte diffusion, better interfacial contact with viscous electrolytes. First, to confirm the advantages of 1-D nanostructured material for the photoelectron collection, we compared the electron transport and charge recombination characteristics between nanoparticle (NP)- and nanorod (NR)-based photoanodes in DSCs by the stepped light-induced transient measurements of photocurrent and voltage (SLIM-PCV). We confirmed that the electron lifetime of the NR-based photoanode was much longer than that of the NP-based photoanode. In addition, highly ordered and vertically oriented TiO2 NT photoanodes were prepared by electrochemical anodization method. We compared the photovoltaic properties of DSCs utilizing TiO2 NT photoanodes prepared by one-step anodization and two-step anodization. And, to reduce the charge recombination rate, energy barrier layer (ZnO, Al2O3)-coated TiO2 NTs also applied in DSC. Furthermore, we applied the TiO2 NT photoanode in DSCs using a viscous electrolyte, i.e., cobalt bipyridyl redox electrolyte, and confirmed that the pore structure of NT array can enhance the performances of this viscous electrolyte.