• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.77-83
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• 1994

Characteristics of hot-electron-induced degradation by AC, DC was investigated for p-MOSFET's(W/L=25/l$\mu$m) with sub-10nm RTP-CVD gate oxides. It was confirmed that the surface channel p-MOSFET of a thinner gate oxide shows less degradation. Mechanisms for this effect were analyzed using a simple MOS Device degradation model. It was found that the number of generated electron traps(fixed charge) is determined by the amount of peak gate current, dependent of the gate oxide thickness, and the major cause of the smaller degradation in the thinner gate oxide devices is the lower hot electron trapping carriers.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.254-257
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• 2008

We have investigated the effect of source/drain electrode deposition method on a performance of top gate structured ZnO TFT performance. TFT using S/D of ITO film, consisted of bi-layer which deposited by ion beam assisted sputtering at the initial stage then deposited by DC magnetron sputtering, showed better performance compared to that using S/D of ITO deposited by just DC magnetron sputtering. Two ITO films exhibited different grain shapes and these resulted in different etching properties. We also suspect that charge trapping on the glass substrate (back channel) during the ITO film deposition may influence the characteristics of top gate structured ZnO TFT.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.19-19
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• 2008

We investigated the programmable memory characteristics of nanoparticle-based memory devices based on the elementary metal nanoparticles (Co and Au) and their binary mixture synthesized by a micellar route to ordered arrays of metal nanoparticles as charge trapping layers. According to the metal nanoparticle species quite different programming/erasing efficiencies were observed, resulting in the tunable memory characteristics at the same programming/erasing bias conditions. This finding will be a good implication for further device scaling and novel device applications since most processes are based on the conventional semiconductor processes.

• ETRI Journal
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• v.31 no.1
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• pp.62-64
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• 2009

We report on the bias stability characteristics of transparent ZnO thin film transistors (TFTs) under visible light illumination. The transfer curve shows virtually no change under positive gate bias stress with light illumination, while it shows dramatic negative shifts under negative gate bias stress. The major mechanism of the bias stability under visible illumination of our ZnO TFTs is thought to be the charge trapping of photo-generated holes at the gate insulator and/or insulator/channel interface.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.883-886
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• 1999

We deposited tungsten gate electrode on gate SiO$_2$by thermal LPCVD with WF$_{6}$, SiH$_4$ and H$_2$. The resistivity was ~10$\mu$Ωcm and exhibited good adhesion ability on oxide when the temperature was higher than 40$0^{\circ}C$. We find that, however, both the low-field current and the charge-trapping characteristics were inferior to the control devices. The oxide degradation by fluorine during the tungsten deposition must be minimized to use the tungsten as alternative gate electrode.e.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.77-83
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• 1994

In this paper we numerically approximated the field-effect mobility of a-Si:H TFT. Field-effect mobility, based on the charge-trapping model and new effective capacitance model in our study, used Chebyshev approximation was approximated as the function of gate potential(gate-to-channel voltage). Even though various external factors are changed, this formula can be applied by choosing the characteristic coefficients without any change of the approximation formula corresponding to each operation region. Using new approximated field-effect mobility formula, the dependences of field-effect mobility on materials and thickness of gate insulator, thickness of a-Si bulk, and operation temperature in inverted staggered-electrode a-Si:H TFT were estimated. By this was the usefulness of new approximated mobility formula proved.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.1943-1950
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• 2009

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.

• Transactions on Electrical and Electronic Materials
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• v.15 no.1
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• pp.37-40
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• 2014

A novel memory is reported, in which $Ge_2Sb_2Te_5$ (GST) has been used as a floating gate. The threshold voltage was shifted due to the phase transition of the GST layer, and the hysteretic behavior is opposite to that arising from charge trapping. Finite Element Modeling (FEM) was adapted, and a new simulation program was developed using c-interpreter, in order to analyze the small shift of threshold voltage. The results show that GST undergoes a partial phase transformation during the process of RESET or SET operation. A large $V_{TH}$ shift was observed when the thickness of the GST layer was scaled down from 50 nm to 25 nm. The novel 1 transistor PCM (1TPCM) can achieve a faster write time, maintaining a smaller cell size.