Transactions on Electrical and Electronic Materials

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Design of Novel 1 Transistor Phase Change Memory

  • Kim, Jooyeon (Faculty of Electrical & Electronic Engineering, Ulsan College) ;
  • Kim, Byungcheul (Department of Electronic Engineering, Gyeongnam National University of Science and Technology (GnTECH))
  • Received : 2013.12.19
  • Accepted : 2013.12.30
  • Published : 2014.02.25
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Abstract

A novel memory is reported, in which $Ge_2Sb_2Te_5$ (GST) has been used as a floating gate. The threshold voltage was shifted due to the phase transition of the GST layer, and the hysteretic behavior is opposite to that arising from charge trapping. Finite Element Modeling (FEM) was adapted, and a new simulation program was developed using c-interpreter, in order to analyze the small shift of threshold voltage. The results show that GST undergoes a partial phase transformation during the process of RESET or SET operation. A large $V_{TH}$ shift was observed when the thickness of the GST layer was scaled down from 50 nm to 25 nm. The novel 1 transistor PCM (1TPCM) can achieve a faster write time, maintaining a smaller cell size.

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References

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