• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.14 no.9
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• pp.749-755
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• 2002

In order to develop a multi-type heat pump system with two indoor units of non-uniform capacities, the optimum refrigerant circuit was developed using capillary tubes. The refrigerant circuit was composed of four main parts, a heating circuit, a cooling circuit, a by-pass circuit and a balance circuit. The system characteristics of multi-type heat pump was investigated through the rating test and the reliability test, using the multi-type psy-chrometric calorimeter. The results of the rating test showed that the capacity of the multi-type heat pump was about 93% of the design value. In particular, the capacity of cooling single mode was about 13% higher than the design value, and the capacity of heating multi mode was about 5% higher than the design value. The reliability of the multi-type heat pump was verified by various reliability tests (overload, extension tube, freeze up, under/over charging, sweat, flood back). The optimal amount of refrigerant charge and compressor capacity were determined from the present work.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.331-338
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• 2014

A charge-pump circuit using a current-bypass technique, which suppresses charge sharing and reduces the sub-threshold currents, helps to decrease phase-locked loop (PLL) jitter without resorting to a feedback amplifier. The PLL shows no stability issues and no power-up problems, which may occur when a feedback amplifier is used. The PLL is implemented in 0.11-${\mu}m$ CMOS technology to achieve 0.856-ps RMS and 8.75-ps peak-to-peak jitter, which is almost independent of ambient temperature while consuming 4 mW from a 1.2-V supply.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2795-2797
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.80-86
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• 2009

In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations and measurements demonstrates that the proposed charge pump exhibits the higher output voltage, the larger output current and a better power efficiency over the traditional twin-well charge pumps.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2798-2800
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• 1999

A new circuit, modified valley fill (MVF) combined with resonant inductor of the self-excited resonant inverter and charge pump capacitors(CPCs), is presented to achieve high PF electronic ballast providing sufficient preheat current to lamp filaments for soft start maintaining low DC bus voltage. The MVF can adjust the valley voltage higher than half the peak line voltage. The CPCs draw the current from the input line to make up the current waveform during the valley interval. The measured PF and THD are 0.99 and 12%, respectively. The lamp current CF is also acceptable in the proposed circuit. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.696-698
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• 2012

This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generate about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1468-1479
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• 2015

Renewable energy resources such as wind and photovoltaic power generation systems demand a high step-up DC-DC converters to convert the low voltage to commercial grid voltage. However, the high step-up converter using a transformer has limitations of high voltage stresses of switches and diodes when the transformer winding ratio increases. Accordingly, conventional studies have been applied to series-connect multioutput converters such as forward-flyback and switched-capacitor flyback to reduce the transformer winding ratio. This paper proposes new single-ended converter topologies of an isolation type and a non-isolation type to improve power efficiency, cost-effectiveness, and output ripple. The first proposal is an isolation-type charge-pump switched-capacitor flyback converter that includes an extreme-ratio isolation switched-capacitor cell with a chargepump circuit. It reduces the transformer winding number and the output ripple, and further improves power efficiency without any cost increase. The next proposal is a non-isolation charge-pump switched-capacitor-flyback tapped-inductor boost converter, which adds a charge-pump-connected flyback circuit to the conventional switched-capacitor boost converter to improve the power efficiency and to reduce the efficiency degradation from the input variation. In this paper, the operation principle of the proposed scheme is presented with the experimental results of the 100 W DC-DC converter for verification.

• Journal of IKEEE
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• v.19 no.4
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• pp.573-582
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• 2015

This paper presents the design of dual mode boost converter for energy harvesting. The designed converter boosts low voltage from energy harvester through a startup circuit. When the voltage goes above predefined value, supplied voltage to startup circuit is blocked by voltage detector. Boost controller makes the boosted voltage into $V_{OUT}$. The proposed circuit consists of oscillator for charge pump, charge pump, pulse generator, voltage detector, and boost controller. The proposed converter is designed and fabricated using a $0.18{\mu}m$ CMOS process. The designed circuit shows that minimum input voltage is 600mV, output is 3V and startup time is 20ms. The boost converter achieves 47% efficiency at a load current of 3mA.

• Journal of Information Display
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• v.7 no.1
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• pp.35-40
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• 2006

Organic light-emitting diode (OLED) display panel using the charge-pump (CP) pixel addressing scheme was fabricated, and the results show that it is applicable for information display. A CP-OLED panel with 64 ${\times}$ 64 pixels consisting of thin-film capacitors and amorphous silicon Schottky diodes was fabricated using conventional thin-film processes. The pixel drive circuit passes electrical current into the OLED cell during most of the frame period as in the thin-film transistor (TFT)-based active-matrix (AM) OLED displays. In this study, the panel was operated at a voltage level of below 4 V, and this operation voltage can be reduced by eliminating the overlap capacitance between the column bus line and the common electrode.