• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.199-201
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• 2008

This paper persents charge/discharge system for small PV using micro-processor. Charge/discharge system designs a Buck converter and using constant voltage charge system because regular voltage is rather high a condenser. Besides, we did compensate for charge voltage of condenser through a temperature compensation circuit. We consists of a 170W stand-alone PV system to observe charge/discharge system character. In the result of search about output character we know that charge and discharge are smoothly running.

• Journal of the Korean Operations Research and Management Science Society
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• v.35 no.3
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• pp.45-58
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• 2010

Due to rapid developments of IT technologies, convergence services like IPTV (Internet protocol television) are shown up. Even though expert and customer had great expectations for this innovative service, commercialization was delayed for years by the legal dispute between industry players. One of the biggest problems was that whether internet backbone providers have to share their internet network backbone with IPTV service providers (which don't have network backbone) or not. As other countries, Korean government set the rules that ISP have to offer indiscriminate access to other IPTV service provider. At the same time, internet backbone providers can charge access charge based on cost by way of compensation. Thus access charge is very critical to the IPTV industry players. The objective of this paper is to provide model that can calculate the reasonable access charge by system dynamics, based upon real data in Korean telecommunication industry.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.315-319
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• 2011

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.25-26
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• 2015

Inductive Power Transfer (IPT) method becomes more and more popular for the Electric Vehicle (EV) battery charger due to its convenience and safety in comparison with plugged-in charger. In recent years, Lithium batteries are increasingly used in EVs and Constant Current/Constant Voltage (CC/CV) charge needs to be adopted for the high efficiency charge. However, it is not easy to design the IPT Battery Charger which can charge the battery with CC/CV charge under the wide range of load variation due to the wide range of variation in its operating frequency. This paper propose a new design and control method which makes it possible to implement the CC/CV mode charge with minimum frequency variation (less than 1kHz) during all over the charge process. A 6.6kW prototype charge has been implemented and 96.1% efficiency was achieved with 20cm air gap between the coils.

• Journal of Power Electronics
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• v.10 no.6
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• pp.769-776
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• 2010

The ultracapacitor module has recently been recast for use in hybrid energy storage systems (HESSs). As a result, accurate state-of-charge (SOC) estimation for an ultracapacitor module is as important as that of primary sources in order to be utilized efficiently in an energy storage system (ESS). However, while SOC estimation via the open-circuit voltage (OCV) method is generally used due to its linear characteristics compared with other ESSs, this method results in many errors in cases of highcurrent charging/discharging within a short time period. Accordingly, this paper introduces a dynamic SOC estimation algorithm that is capable of SOC compensation of an ultracapacitor module even when there is a current input and output. A cycle profile that simulates the operating conditions of a mild-HEV was applied to a vehicle simulator to verify the effectiveness of the proposed algorithm.

• Journal of Cadastre & Land InformatiX
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• v.45 no.2
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• pp.27-44
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• 2015

The Cadastral Resurvey Project implementation process must make some landowner better off (area increase) and others worse off (area decrease) by changing the boundaries of ones' own land. This study focuses on the Standard way to calculate compensation if landlords are worse off or charge otherwise. For this study, we analyze the compensation by comparing appraisal value method and a method based on the individual land value by public announcement in theoretic manner. we collected considerable amount of data on both appraisal values and the individual land values by public announcement. We found the difference of compensation between appraisal value method and a method based on the individual land value by public announcement. In this study, more desirable and efficient implementation strategy for government agency who is in charge of cadastral project nationwide is suggested.

• Korean Journal of Metals and Materials
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• v.56 no.11
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• pp.822-828
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• 2018

P-type Ce/Yb-filled skutterudites were synthesized, and their charge transport and thermoelectric properties were investigated with partial double filling and charge compensation. In the case of $(Ce_{1-z}Yb_z)_{0.8}Fe_4Sb_{12}$ without Co substitution, the marcasite ($FeSb_2$) phase formed alongside the skutterudite phase, but the generation of the marcasite phase was inhibited by increasing Co concentration. The electrical conductivity decreased with increasing temperature, exhibiting degenerate semiconductor behavior. The Hall and Seebeck coefficients were positive, which confirmed that the specimens were p-type semiconductors with holes as the major carriers. The carrier concentration decreased as the concentration of Ce and Co increased, which led to decreased electrical conductivity and increased Seebeck coefficient. The thermal conductivity decreased due to a reduction in electronic thermal conductivity via Co substitution, and due to decreased lattice thermal conductivity via double filling of Ce and Yb. $(Ce_{0.25}Yb_{0.75})_{0.8}Fe_{3.5}Co_{0.5}Sb_{12}$ exhibited the greatest dimensionless figure of merit (ZT = 0.66 at 823 K).

• Journal of Information Display
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• v.3 no.3
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• pp.30-34
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• 2002

CRTs can be improved by means of magnetic quadrupoles. Areas of improvement are convergence, spot shape, image-flatness and space charge compensation.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.2
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• pp.101-107
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• 2009

This paper deal with development of on-line type voltage sag compensation system using supercapacitor EDLC to solve the voltage sag problems which are considered to be dominant disturbances affecting the power quality. With the wide use of semiconductor devices in electrical equipment, modem-type loads are becoming increasingly sensitive to the voltage sags and the disturbances prove to be costly to industries. Supercapacitor EDLC is employed to compensate dynamically for the voltage sag of system with sensitive loads. This capacitor has higher energy density than the electrolytic capacitor. Also, this capacitor has a lot of advantage such as no maintenance, longer life cycle and faster charge-discharge time than the battery system. Therefore, in this paper, the energy design scheme of supercapacitor and the configuration technique of on-line type voltage sag compensation systems are newly introduced. According to the results of experimental of prototype 5[kVA] system, it is verified that the developed system has effectiveness of voltage sag compensation by using a supercapacitor EDLC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.