• ETRI Journal
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• v.41 no.6
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.9
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• pp.634-642
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• 2001

We calculate the facet reflectivity of buried channel waveguides and ridge waveguides as a function of the waveguide width for various thicknesses using the angular spectrum method and the two dimensional field profiles obtained by the variational method (VM) and the effective index method (EIM). The variation of the reflectivity of buried channel waveguides as a function of the waveguide width is large, while that of ridge waveguides is very small. The accuracy of the field profiles necessary for the calculation of the facet reflectivity using the angular spectrum method greatly affects that of the facet reflectivity. The difference between the exact reflectivity and that using EIM increases as the waveguide width and thickness decreases due to the inaccuracy of the field profiles obtained by EIM. However, the difference between the exact reflectivity and that using VM is smaller than that using EIM regardless of waveguide width and thickness. The difference between the facet reflectivities u sing EIM and VM is small in the area where the EIM works very well.

• Journal of the Optical Society of Korea
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• v.7 no.4
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• pp.269-274
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• 2003

In this paper, a Gaussian apodization technique applied to a transmission volume hologram for holographic demultiplexer is proposed. The Gaussian apodized grating of 15 mm ${\times}$ 11mm size, $38{\mu}m$ thickness and 3.2 mm horizontal standard deviation of the Gaussian index modulation profile was fabricated. A 22-channel demultiplexer based on that grating has been optically demonstrated. The channel spacing, the interchannel cross-talk level and the channel uniformity of 0.8 nm, -30 dB and 1.5 dB, respectively, were obtained.

• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.363-367
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• 1988

A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.855-858
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• 2001

The stress induced leakage currents of thin silicon oxides is investigated in the VLSI implementation of a self learning neural network integrated circuits using a linearity synapse transistor. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 41 ${\AA}$, 86${\AA}$, which have the channel width ${\times}$ length 10 ${\times}$1${\mu}$m, 10 ${\times}$0.3${\mu}$m respectively. The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.10
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• pp.53-59
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• 1997

In this paper, we present a 20 GHz low-loss dual-mode channel filter designed by using mode matching method. The performance of dual-mode channel filter mainly depends on iris characteristics. Therefore the exact design of iris is the key point to get good frequncy response of the filter. MOde matching technique is widely used ot design several kinds of waveguide filters because it is simple in theory and can easily calculate the scattering matrices at the discontinuities with simple structure like iris coupled filters. Additionally the effect for finite thickness of the iris in the dual-mode cavity iflter is analyzed by te full-wave method, providing the exact filter implementation without trial and error.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.69-75
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• 1997

A Si-channle MESFET using .delta.-doped layers was designed and the considerable enhancement of the current driving capability of the device was observed by simulation. The channel consists of double .delta.-doped layers separated by a low-doped spacer. Cariers are spilt from the .delta.-doped layers and are accumulated in the spacer. The saturation current is enhanced by the contribution of the carriers in the spacer. Among the design parameters that affect the peformance of the device, the thickness of the spacer and the ratio of the doping concentrations of the two .delta.-doped layers were studied. The spacer thickenss of 300~500.angs. and the doping ratio of 3~4 were shown to be the optimized values. The saturation current was observed to be increased by 75% compared with a bulk-channel MESFET. The performances of transconductance, output resistance, and subthreshold swing were also enhanced.

• Advances in Computational Design
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• v.1 no.2
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• pp.207-220
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• 2016

The aim of this study is to investigate the effect of stiffened element and edge stiffener in the behaviour and flexural strength of built-up cold-formed steel beams. An experimental and analytical analysis of CFS channel sections in four different geometries is conducted, including simple channel sections, a stiffened channel section with or without edge stiffeners. Nonlinear finite element models are developed using finite element analysis software package ANSYS. The FEA results are verified with the experimental results. Further, the finite element model is used for parametric studies by varying the depth, thickness, and the effect of stiffened element, edge stiffener and their interaction with compression flanges on stiffened built-up cold-formed steel beams with upright edge stiffeners. In addition, the flexural strength predicted by the finite element analysis is compared with the design flexural strength calculated by using the North American Iron and Steel Institute Specifications for cold-formed steel structures (AISI: S100-2007) and suitable suggestion is made.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.61-65
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• 2010

Threshold voltage is one of the most important factors in a device modeling. In this paper, analytical method to calculate threshold voltage for recessed channel (RC) MOSFETs is studied. If we know the fundamental parameter of device, such as radius, oxide thickness and doping concentration, threshold voltage can be obtained easily by using this model. The model predicts the threshold voltage which is the result of 2D numerical device simulation.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.6
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• pp.401-415
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• 1989

A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.