• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• Electrical & Electronic Materials
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• v.7 no.1
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• pp.7-14
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• 1994

Structural and optical characteristics in $SnO_2$/a-Se/Al sample by aging variation and applying constant voltage had been investigated. a-Se was varied with monoclinic structure and its surface was greatly exchanged. Its capacitance was first decreased and then increased and its photo-current, photo-voltage and photo-capacitance were increased gradually with day and applying voltage. From the results, crystallization of a-Se and dopant trap level formation had been identified. Also, it was acknowledged $SnO_2$/a-Se/Al sample is useful in photovoltaic and solid thin film cell.

• ETRI Journal
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• v.26 no.6
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• Journal of IKEEE
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• v.24 no.3
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• pp.845-852
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• 2020

Developing standard cells for 3nm and beyond requires significant advances in the device and interconnect technology. Thus, it is very important to quantify the impact of the new technology in various aspects. In this paper, we perform a through analysis on the impact of Buried Power Rail (BPR) and Complementary FET (CFET) in the perspective of cell area and parasitics such as capacitance. We emphasize that CFET is a technology that realizes 4T and beyond for standard cell designs, but significant capacitance increases (+18.0%), compared to its counterpart technology (FinFET) cell, due to the increase of cell height in the Z-direction.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.8
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• pp.775-780
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• 2013

In general, the battery module of an electric vehicle (EV) consists of lithium-ion cells. A lithium-ion battery is a secondary rechargeable battery, and it consists of numerous stacked plates that serve as electrodes and separators. Owing to these microstructural features, its numerical analysis is very expensive. Therefore, this study aims to present a simplified thermal analysis model using equivalent thermal properties, and we compare the experimental results with numerical results for 185.3Ah and 20Ah cells. Furthermore, we show the thermal behavior of cells without the finite element method (FEM) or finite volume method (FVM) by adopting the lumped capacitance method (LCM).

• Journal of Power Electronics
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• v.12 no.1
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• pp.40-48
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• 2012

This paper proposes the State-of-charge (SOC) estimator of a LiPB Battery using the Extended Kalman Filter (EKF). EKF can work properly only with an accurate model. Therefore, the high accuracy electrical battery model for EKF state is discussed in this paper, which is focused on high-capacity LiPB batteries. The battery model is extracted from a single cell of LiPB 40Ah, 3.7V. The dynamic behavior of single cell battery is modeled using a bulk capacitance, two series RC networks, and a series resistance. The bulk capacitance voltage represents the Open Circuit Voltage (OCV) of battery and other components represent the transient response of battery voltage. The experimental results show the strong relationship between OCV and SOC without any dependency on the current rates. Therefore, EKF is proposed to work by estimating OCV, and then is converted it to SOC. EKF is tested with the experimental data. To increase the estimation accuracy, EKF is improved with a single dominant varying parameter of bulk capacitance which follows the SOC value. Full region of SOC test is done to verify the effectiveness of EKF algorithm. The test results show the error of estimation can be reduced up to max 5%SOC.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.124-127
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• 2000

The purpose of this study is to research and develop PAn-Carbon composite electrode for Supercapacitor. Supercapacitor cell of PAn-Carbon composite electrode with 1M $LiClO_{4}/IPC$ brings out good capacitor performance below 4.0V. The radius of semicircle of PAn-Carbon composite electrode adding 30wt% Acetylene Black was absolutely small. The total resistance of Supercapacitor cell mainly depended on internal resistance of he electrode. The discharge capacitance of PAn-Carbon on composite with 30wt% Acetylene Black in 1st and 50th cycles was 29 and 31F/g at current density of $1mA/cm^2$. The capacitance of PAn-Carbon composite with 30wt% Acetylene Black capacitor was larger than that of PAn capacitor without Acetylene Black. The coulombic efficiency of supercapacitor at discharge process of 1 and 50 cycles were 94 and 100%. respectively. PAn-Carbon composite Supercapacitor with 30wt.% Acetylene Black content showed good capacitance and stability with cycling.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.235-238
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• 2003

Photovoltaic(PV) array, which is generally installed outside, has the possibility to be damaged by high voltage due to lightning. Because the surge characteristics of PV array have not b eon fully Identified yet, there is a very important issue whether PV array should be connected with ground or not. In this paper, a basic model of PV array is provided considering the PV cell's barrier capacitance and ground capacitance for analysis of surge characteristics.

• Bulletin of the Korean Chemical Society
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• v.31 no.12
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• pp.3852-3855
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• 2010

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.4
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• pp.247-255
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• 2018

This paper proposes a transformer design of a direct cell-to-cell active cell balancing circuit with a multi-winding transformer for battery management system (BMS) applications. The coupling coefficient of the multi-winding transformer and the output capacitance of MOSFETs significantly affect the balancing current transfer efficiency of the cell balancing operation. During the operation, the multi-winding transformer stores the energy charged in a specific source cell and subsequently transfers this energy to the target cell. However, the leakage inductance of the multi-winding transformer and the output capacitance of the MOSFET induce an abnormal energy transfer to the non-target cells, thereby degrading the transfer efficiency of the balancing current in each cell balancing operation. The impacts of the balancing current transfer efficiency deterioration are analyzed and a transformer design methodology that considers the coupling coefficient is proposed to enhance the transfer efficiency of the balancing current. The efficiency improvements resulting from the selection of an appropriate coupling coefficient are verified by conducting a simulation and experiment with a 1 W prototype cell balancing circuit.