• The Journal of the Korea Contents Association
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• v.7 no.2
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.63-70
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• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Asian-Australasian Journal of Animal Sciences
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• v.10 no.1
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• pp.47-53
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• 1997

Appropriation of partial substitution of concentrate mixture by urea-molasses-mineral block (UMMB) lick supplements for 20 lactating crossbred cows in 2nd and 3nd lactation was studied. Animals fed on wheat straw ad lib. and Berseem (Trifolium alaxandrium) fodder @ 1.5 kg/d on dry matter basis. Animals of control group were given concentrate supplement, while in treatment groups 10% of the concentrate requirement was substituted with 3 different types of UMMB lick type A ($T_1$), type B ($T_2$) and type C ($T_3$). CP content of the ration was 15%. Total dry matter intake (DMI) was about 1.0 kg/kg of fat corrected milk (FCM) yield and was not significantly different between control and treatment groups. Digestibility of neither proximate principles nor cell wall constituents were deviated on UMMB licks partial supplementation. FCM yield was increased by 140, 410 and 460 g/d, in $T_1$, $T_2$ and $T_3$, respectively, in comparison to control group but differences were statistically invalid. Though fat per cent was reduced, fat yields were remain constant among treatments. Milk composition was unaltered except significant difference (p < 0.01) in non-protein nitrogen (NPN) content. Gross-N and digestible-N conversion was significantly higher (p < 0.01) with $T_1$, $T_2$ and $T_3$ than control group. Energy utilization efficiency for milk production was only 36%. Result demonstrated that UMMB licks could be partial supplemented up to 10% of the concentrate requirement of crossbred cows yielding on an average 14kg/d without any adverse effect on feed intake, nutrient utilization and mild production. Comparatively, UMMB lick type B and C was proved better than type A and also economically viable.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.798-803
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.1li wireless LAN security. To maximize its performance, two AES cores ate used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about $20\%$ compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 13,360 gates, and the estimated throughput is about 168 Mbps at 54-MHz clock frequency. The functionality of the CCMP core is verified by Excalibur SoC implementation.

• The Korean Journal of Physiology and Pharmacology
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• v.18 no.4
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• pp.341-346
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• 2014

Lubiprostone is a chloride ($Cl^-$) channel activator derived from prostaglandin $E_1$ and used for managing constipation. In addition, lubiprostone affects the activity of gastrointestinal smooth muscles. Interstitial cells of Cajal (ICCs) are pacemaker cells that generate slow-wave activity in smooth muscles. We studied the effects of lubiprostone on the pacemaker potentials of colonic ICCs. We used the whole-cell patch-clamp technique to determine the pacemaker activity in cultured colonic ICCs obtained from mice. Lubiprostone hyperpolarized the membrane and inhibited the generation of pacemaker potentials. Prostanoid $EP_1$, $EP_2$, $EP_3$, and $EP_4$ antagonists (SC-19220, PF-04418948, 6-methoxypyridine-2-boronc acid N-phenyldiethanolamine ester, and GW627368, respectively) did not block the response to lubiprostone. L-NG-nitroarginine methyl ester (L-NAME, an inhibitor of nitric oxide synthase) and 1H-[1,2,4]oxadiazolo[4,3,-a]quinoxalin-1-one (ODQ, an inhibitor of guanylate cyclase) did not block the response to lubiprostone. In addition, tetraethylammonium (TEA, a voltage-dependent potassium [$K^+$] channel blocker) and apamin (a calcium [$Ca^{2+}$]-dependent $K^+$ channel blocker) did not block the response to lubiprostone. However, glibenclamide (an ATP-sensitive $K^+$ channel blocker) blocked the response to lubiprostone. Similar to lubiprostone, pinacidil (an opener of ATP-sensitive $K^+$ channel) hyperpolarized the membrane and inhibited the generation of pacemaker potentials, and these effects were inhibited by glibenclamide. These results suggest that lubiprostone can modulate the pacemaker potentials of colonic ICCs via activation of ATP-sensitive $K^+$ channel through a prostanoid EP receptor-independent mechanism.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.8
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• pp.62-69
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• 2010

Many electric poles in the softground have been collapsed due to external load. In this study, 10 types of tests were performed with variation of location, numbers and depths of anchor blocks as well as depth of poles to find horizontal earth pressure through full scale pull-out tests. The horizontal earth pressure increased with embedded depth of electric pole, and earth pressure of lower passive zone decreased. The deeper of anchor block, earth pressure of passive zone becomes less. 4 anchor blocks decreased earth pressure at G.L.-0.9[m]. It is considered that 4 anchor blocks installed along 80[cm] vertically are main reason. Overall, when more anchor blocks are constructed, excavation area is large, and constructivity such as backfill is bad, therefore one anchor block would be preferred.