• Journal of Power Electronics
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• 제16권2호
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• pp.532-541
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• 2016

A single-phase asymmetrical cascaded multilevel inverter is introduced with the goal of increasing power quality with the reduction of power in insulated-gate bipolar transistor (IGBT) switches. In the present work, the proposed inverter topology is analyzed and generalized with respect to different proposed algorithms for choosing different voltage source values. To prove the advantages of the proposed inverter, a case study involving a 17-level inverter is conducted. The simulation and experimental results with reduced THD are also presented and compared with the MATLAB/SIMULINK simulation results. Finally, the proposed topology is compared with different multilevel inverter topologies available in the literature in terms of the number of IGBT switches required with respect to the number of levels generated in the output of inverter topologies.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권11호
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• pp.645-651
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• 2002

In this paper, a multilevel PWM inverter employing a cascaded transformer is presented to reduce the harmonics of output voltage and load currents. The proposed PWM inverter consists of two full-bridge modules and their corresponding transformers. The secondarics of each transformer are series-connected. So continuous output voltage levels can be synthesized from the suitable selection of the turns ratio of trasformer. And it appears an integral ratio to input DC source. Because of the cascaded connection of transformers, output filter inductor is not necessary. The operational principles and analysis are explained, and it is compared with a conventional isolated H-bridge PWM inverter. The validity of proposed multilevel inverter is verified through simulated and experimental waveform and their FFT results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 전력전자학술대회 논문집
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• pp.532-533
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• 2013

본 논문에서는 다단 멀티레벨 컨버터(Cascaded Multilevel Converter) 방식으로 개발된 STATCOM에서 Phase-Shifted PWM 시 발생할 수 있는 개별 Cell 인버터의 출력 전압 위상 지연을 보상하여 시스템의 성능을 개선하였다.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.576-588
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• 2014

The superiority of CMI (Cascaded Multilevel Inverter) is unparalleled in high power and high voltage STATCOM (Static Synchronous Compensator). However, the parameters and operating conditions of each individual power unit composing the cascaded STATCOM differ from unit to unit, causing unit voltage disequilibrium on the DC side. This phenomenon seriously impairs the operation performance of STATCOM, and thus maintaining the DC voltage balance and stability becomes critical for cascaded STATCOM. This paper analyzes the case of voltage disequilibrium, combines the operation characteristics of the cascaded STATCOM, and proposes a new DC voltage control scheme with the advantages of good control performance and stability. This hierarchical control method uses software to achieve the total active power control and also uses chopper controllers to enable that the imbalance power can flow among the capacitors in order to keep DC capacitor voltages balance. The operating principle of the chopper controllers is analyzed and the implementation is presented. The major advantages of the proposed control strategy are that the number of PI regulators has been decreased remarkably and accordingly the blindness of system design and debugging also reduces obviously. The simulation reveals that the proposed control scheme can achieve the satisfactory control goals.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1163-1164
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• 2011

Cascaded H-bridge 멀티레벨인버터의 구동을 위해서는 독립된 입력전압원의 확보가 필요하다. 본 논문에서는 이러한 Cascaded H-bridge 멀티레벨 인버터의 구조적 제약을 극복하기 위해 Buck-boost 컨버터와 Flyback 컨버터의 결합을 이용한 단일입력전원 구동 방법을 제안한다. 제안된 회로의 이론적 분석을 수행하고 시뮬레이션을 통하여 타당성을 검증한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.387-388
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• 2017

Cascaded H-bridge 멀리레벨인버터는 출력전압 레벨 수를 증가시켜 고전압 응용이 가능하도록 하는 전력변환장치로 모듈화 특성이 우수하여 그 활용 범위를 넓혀가고 있다. 출력 전압레벨 수를 증가시켜 보다 정현파에 가까운 양질의 출력전압을 생성하기 위해서는 스위칭 소자와 입력 전압원 개수의 증가로 인해 회로구조와 제어방법이 복잡해지는 문제가 발생한다. 하지만 스위칭 여유율(Redundancy)에 따른 대체 스위칭 패턴의 적용으로 전체 시스템의 신뢰성을 개선시킬 수도 있다. 본 논문에서는 고장나무 분석을 통해 Cascaded H-bridge 멀티레벨 인버터의 위험도를 계산하고 스위칭 여유율과의 관련성을 분석하고자 한다.

• Journal of Power Electronics
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• 제18권2호
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• pp.522-532
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• 2018

The cascaded H Bridge (CHB) multilevel inverter (MLI) is popular among the classical MLI topologies due to its modularity and reliability. Although space vector modulation (SVM) is the most suitable modulation scheme for MLIs, it has not been used widely in industry due to the higher complexity involved in its implementation. In this paper, a simple and novel generalized SVM algorithm is proposed, which has both reduced time and space complexity. The proposed SVM involves the generalization of both the duty cycle calculation and switching sequence generation for any n-level inverter. In order to generate the gate pulses for an inverter, a generalized switch matrix (SM) for the CHB inverter is also introduced, which further simplifies the algorithm. The algorithm is tested and verified for three-phase, three-level and five-level CHB inverters in simulations and hardware implementation. A comparison of the proposed method with existing SVM schemes shows the superiority of the proposed scheme.

• Journal of Power Electronics
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• 제10권3호
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• pp.262-269
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• 2010

This paper proposes a practical design for a Cascaded H-Bridge Multilevel (CHBM) inverter based on Power Electronics Building Blocks (PEBB) and high performance control to improve current control and increase fault tolerance. It is shown that the expansion and modularization characteristics of the CHBM inverter are improved since the individual inverter modules operate more independently, when using the PEBB concept. It is also shown that the performance of current control can be improved with voltage delay compensation and the fault tolerance can be increased by using unbalance three-phase control. The proposed design and control methods are described in detail and the validity of the proposed system is verified experimentally in various industrial fields.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1552-1557
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• 2015

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

• Journal of Power Electronics
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• 제10권1호
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• pp.34-42
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• 2010

Reliability is an important issue in cascaded H-bridge converters (CHB converters) because they use a high number of power semiconductors. A faulty power cell in a CHB converter can potentially lead to expensive downtime and great losses on the consumer side. With a fault-tolerant control strategy, operation can continue with the undamaged cells; thus increasing the reliability of the system. In this paper, the operating principles and the control method for a CHB multilevel rectifier are introduced. The influence of various faults on the CHB converter is investigated. The method of fault diagnosis and the bypassing of failed cells are explained. A fault-tolerant protection strategy is proposed to achieve redundancy in the CHB rectifier. The redundant H-bridge concept helps to deal with device failures and to increase system reliability. Simulation results verify the performance of the proposed strategy.