• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1328-1336
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• 2013

Nowadays multilevel inverters are developing generally due to reduced voltage stress on power switches and low total harmonic distortion (THD) in output voltage. However, for increasing the output voltage levels the number of circuit devices are increased and it results in increasing the cost of converter. In this paper, a novel multilevel inverter is proposed. The suggested topology uses less number of power switches and related gate drive circuits to generate the same level in output voltage with comparison to traditional cascaded multilevel inverter. With the proposed topology all levels in output voltage can be realized. As an illustration, a symmetric 13-level and asymmetric 29-level proposed inverters have been simulated and implemented. The total peak inverse (PIV) and power losses of presented inverter are calculated and compared with conventional cascaded multilevel inverter. The presented analyses show that the power losses in the suggested multilevel inverter are less than the traditional inverters. Presented simulation and experimental results demonstrate the feasibility and applicability of the proposed inverter to obtain the maximum number of levels with less number of switches.

• Journal of Power Electronics
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• v.18 no.2
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• pp.522-532
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• 2018

The cascaded H Bridge (CHB) multilevel inverter (MLI) is popular among the classical MLI topologies due to its modularity and reliability. Although space vector modulation (SVM) is the most suitable modulation scheme for MLIs, it has not been used widely in industry due to the higher complexity involved in its implementation. In this paper, a simple and novel generalized SVM algorithm is proposed, which has both reduced time and space complexity. The proposed SVM involves the generalization of both the duty cycle calculation and switching sequence generation for any n-level inverter. In order to generate the gate pulses for an inverter, a generalized switch matrix (SM) for the CHB inverter is also introduced, which further simplifies the algorithm. The algorithm is tested and verified for three-phase, three-level and five-level CHB inverters in simulations and hardware implementation. A comparison of the proposed method with existing SVM schemes shows the superiority of the proposed scheme.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1670-1682
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• 2018

The further improvement of submarine propulsion is associated with the modularity of accumulator-fed inverters, such as cascaded inverters (CIs). CI technology guarantees smooth output voltages with reduced switch frequencies under linear loads. However, the output voltages of CIs are distorted under rectifier loads. This distortion requires harmonic suppression technology. One such technology is the repetitive controller (RC), which is commonly applied but suffers from poor performance in propulsion systems. In this study, the FFT spectrum of a CI under rectifier load is analyzed, and the harmonic contents are uneven in magnitude. For the purpose of harmonic suppression, the control gains at each harmonic frequency should be seriously considered. A RC with a specific harmonic gain compensation (SHGC) for CIs is proposed. This method provides additional control gains at low-order harmonic frequencies, which are difficult to achieve with conventional RCs. This SHGC consists of a band-pass filter (BPF) and proportional element and is easy to implement. These features make the proposed method suitable for submarine propulsion. Experimental results verify the feasibility of the improved RC.

• Journal of Power Electronics
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• v.16 no.1
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• pp.173-181
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• 2016

In this paper, a new technique for harmonic optimization in cascaded H-bridge 7-level inverters is proposed. The suggested strategy is based on minimizing an objective function which simultaneously optimizes the converter utilization and Total Harmonic Distortion (THD). The Switch Utilization Ratio (SUR) is formulized for both the phase and line-line voltages of a 7-level inverter and is considered in the final objective functions. Based upon the SUR formula, utilization ratio enhancement will reduce the value of feeding DC links, which improves the efficiency and lifetime of the circuit components due to lower voltage stresses and losses. In order to achieve more effective solution in different modulation indices, it is assumed that the DC sources can be altered. Experimental validation is presented based on a three-phase 7-level inverter prototype.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1610-1620
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• 2015

A major problem in conventional multilevel inverter is that an increase in power semiconductor switches causes an increase in cost and switching losses of the inverter. The multicarrier strategy adopted for the multilevel inverters has become more popular due to reduced cost, lower harmonic distortion, and higher voltage capability than the conventional switching strategy applied to inverters. Various topologies and modulation strategies have been reported for utility and drive applications. Level shifted based pulse width modulation techniques are proposed to investigate the performance of the multilevel inverter. The proposed work focuses on reducing the utilized switches so that the cost and the switching losses of the inverter do not go up and the consistent efficiency could be achieved. This paper presents the detailed analysis of these topologies. The analysis is based on the number of switches, DC sources, output level, maximum voltage, and the efficiency. As an illustration, single phase cascaded multilevel inverter topologies are simulated using MATLAB/SIMULINK and the experimental results demonstrate the viability of these inverters.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.5
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• pp.718-725
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• 2015

This paper proposes a novel level-shifted PWM (LS-PWM) strategy for fault tolerant cascaded multilevel inverter. Most proposed fault-tolerant operation methods in many of studies are based on a phase-shifted PWM (PS-PWM) method. To apply these methods to multilevel inverter systems using LS-PWM, two additional steps will be implemented. During the occurrence of a single-inverter-cell fault, the carrier bands scheme is reconfigured and modulation levels of inverter cells are reassigned in this proposed fault-tolerant operation. The proposed strategy performs balanced three-phase line-to-line voltages and line currents when a switching device fault occurs in a cascaded multilevel inverter using LS-PWM. Simulation and experimental results are included in the paper to verify the proposed method.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.229-236
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• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1458-1466
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• 2019

Multilevel inverters have appeared as a successful and utilitarian solution in many power applications. The prime objective of an inverter is to keep the fundamental component of the output voltage of a multilevel inverter at a preferred value. Equally important is the need to keep the harmonic components in the output voltage within stated harmonic limits. Therefore, the basis of this research is to develop a harmonic minimization function that optimizes the switching angles of cascaded H-bridge multilevel inverter. Due to benefits of the Cuckoo Search (CS) algorithm, it is applied to determine the switching angles, which are further used to generate the switching pattern for firing the H-bridges of multilevel inverter. Simulation results are compared with SPWM based firing scheme. The switching frequency for SPWM firing scheme is taken as 200 Hz since the switching losses are increased when switching frequency is high. To validate the ability of Cuckoo Search optimized firing scheme in minimization of harmonics, experimental results obtained from hardware prototype of Five Level Cascaded H-Bridge Multilevel Inverter equipped with a FPGA controller are presented to verify the simulation results.

• Journal of Power Electronics
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• v.19 no.1
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• pp.244-253
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• 2019

Finite control set model-predictive control (FCS-MPC) has received increasing attentions due to its outstanding dynamic performance. It is being widely used in power converters and multilevel inverters. However, FCS-MPC requires a lot of calculations, especially for multilevel-cascaded H-bridge (CHB) static synchronous compensators (STATCOMs), since it has to take account of all the feasible voltage vectors of inverters. Hence, an improved five-segment space vector pulse width modulation (SVPWM) method based on the non-orthogonal static reference frames is proposed. The proposed SVPWM method has a lower number of switching states and requires fewer computations than the conventional method. As a result, it makes FCS-MPC more efficient for multilevel cascaded H-bridge STATCOMs. The partial cost function is adopted to sequentially solve for the reference current and capacitor voltage. The proposed FCS-MPC method can reduce the calculation burden of the FCS-MPC strategy, and reduce both the switching frequency and power losses. Simulation and experimental results validate the excellent performance of the proposed method when compared with the conventional approach.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.12
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• pp.133-140
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• 2013

Cascaded H-Bridge multi-level inverters can be implemented through the series connection of single-phase modular power bridges. In recent years, multi-level inverters are becoming increasingly popular for high power applications due to its improved harmonic profile and increased power ratings. This paper presents a control method for balancing the dc-link voltage and ride-through enhancement, a modified pulse width-modulation Compensation algorithm of cascaded H-bridge multi-level inverters. During an under-voltage protection mechanism, causing the system to shut down within a few milliseconds after a power interruption in the main input sources. When a power interruption occurs finish, if the system is a large inertia restarting the load a long time is required. This paper suggests modifications in the control algorithm in order to improve the sag ride-through performance of ac inverter. The new proposed strategy recommends maintaining the DC-link voltage constant at the nominal value during a sag period, experimental results are presented.