• Title/Summary/Keyword: Carrier frequency offset

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Implemetation of OFDM Ethernet Modem System (고속이동체를 위한 OFDM Ethernet 모뎀 시스템 구현)

  • Jeong, Sang-Guk;An, Tae-Ki;Kim, Back-Hyun;Nam, Myung-Woo;Lee, Yong-Seok;Oh, Myung-Kwan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.4
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    • pp.1817-1823
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    • 2011
  • OFDM Modulation is used for multimedia transmission At Urban Train. Recently the application field about data transmission is expanding the image as well. The case which the number of OFDM carrier is big is advantageous because multipass fading is big 18GHz wireless frequency. Existing WLAN which an ethernet transmission is possible is not suitable to a great distance transmission because number of carrier is 64. In this paper, we developed OFDM modem suitable to transmit broadband data at high speed train. A doppler compensation block added to offset the doppler effect. Therefore, the effectiveness is expected to be very big in field of urban train.

A Design of 5.8 ㎓ Oscillator using the Novel Defected Ground Structure

  • Joung, Myoung-Sub;Park, Jun-Seok;Lim, Jae-Bong;Cho, Hong-Goo
    • Journal of electromagnetic engineering and science
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    • v.3 no.2
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    • pp.118-125
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    • 2003
  • This paper presents a 5.8-㎓ oscillator that uses a novel defected ground structure(DGS), which is etched on the metallic ground plane. As the suggested defected ground structure is the structure for mounting an active device, it is the roles of a feedback loop inducing a negative resistance as well as a frequency-selective circuit. Applying the feedback loop between the drain and the gate of a FET device produces precise phase conversion in the feedback loop. The equivalent circuit parameters of the DGS are extracted by using a three-dimensional EM simulation ,md simple circuit analysis method. In order to demonstrate a new DGS oscillator, we designed the oscillator at 5.8-㎓. The experimental results show 4.17 ㏈m output power with over 22 % dc-to-RF power efficiency and - 85.8 ㏈c/Hz phase noise at 100 KHz offset from the fundamental carrier at 5.81 ㎓.

Asynchronous Multilevel Search Strategy for Fast Acquisition of AltBOC Signals

  • Kim, Binhee;Kong, Seung-Hyun
    • Journal of Positioning, Navigation, and Timing
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    • v.4 no.4
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    • pp.161-171
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    • 2015
  • Alternative binary offset carrier (AltBOC) signals can be approximated by four synchronized direct sequence spread spectrum (DSSS) signals, each pair of which is a quadrature phase shift keyed (QPSK) signal at a different frequency. Therefore, depending on the strength of an incoming AltBOC signal, an acquisition technique can reduce the mean acquisition time (MAT) by searching the four DSSS signals asynchronously; the search for each of the four DSSS signals can start at one of the evenly separated hypotheses on the two-dimensional hypothesis space. And detection sensitivity can be improved by multiple levels when different numbers of search results for the same hypothesis are combined. In this paper, we propose a fast AltBOC acquisition technique that has an asynchronous search strategy and efficiently utilizes the output of the four search results to increase the sensitivity level when sensitivity improvement is needed. We provide a complete theoretical analysis and demonstrate with numerous Monte Carlo simulations that the MAT of the proposed technique is much smaller than conventional AltBOC acquisition techniques.

Performance Degradation Due to Particle Impoverishment in Particle Filtering

  • Lim, Jaechan
    • Journal of Electrical Engineering and Technology
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    • v.9 no.6
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    • pp.2107-2113
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    • 2014
  • Particle filtering (PF) has shown its outperforming results compared to that of classical Kalman filtering (KF), particularly for highly nonlinear problems. However, PF may not be universally superior to the extended KF (EKF) although the case (i.e. an example that the EKF outperforms PF) is seldom reported in the literature. Particularly, PF approaches show degraded performance for problems where the state noise is very small or zero. This is because particles become identical within a few iterations, which is so called particle impoverishment (PI) phenomenon; consequently, no matter how many particles are employed, we do not have particle diversity regardless of if the impoverished particle is close to the true state value or not. In this paper, we investigate this PI phenomenon, and show an example problem where a classical KF approach outperforms PF approaches in terms of mean squared error (MSE) criterion. Furthermore, we compare the processing speed of the EKF and PF approaches, and show the better speed performance of classical EKF approaches. Therefore, PF approaches may not be always better option than the classical EKF for nonlinear problems. Specifically, we show the outperforming result of unscented Kalman filter compared to that of PF approaches (which are shown in Fig. 7(c) for processing speed performance, and Fig. 6 for MSE performance in the paper).

LC VCO using dual metal inductor in $0.18{\mu}m$ mixed signal CMOS process

  • Choi, Min-Seok;Jung, Young-Ho;Shin, Hyung-Cheol
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.503-504
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    • 2006
  • This paper presents the design and fabrication of a LC voltage-controlled oscillator (VCO) using 1-poly 6-metal mixed signal CMOS process. To obtain the high-quality factor inductor in LC resonator, patterned-ground shields (PGS) is placed under the symmetric inductor to reduce the effect from image current of resistive Si substrate. Moreover, due to the incapability of using thick top metal layer of which the thickness is over $2{\mu}m$, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via materials along the metal traces is adopted. The circuit operated from 2.63 GHz to 3.09 GHz tuned by accumulation-mode MOS varactor. The corresponding tuning range was 460 MHz. The measured phase noise was -115 dBc/Hz @ 1MHz offset at 2.63 GHz carrier frequency and the current consumption and the corresponding power consumption were about 2.6 mA and 4.68 mW respectively.

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Low Computational FFT-based Fine Acquisition Technique for BOC Signals

  • Kim, Jeong-Hoon;Kim, Binhee;Kong, Seung-Hyun
    • Journal of Positioning, Navigation, and Timing
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    • v.11 no.1
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    • pp.11-21
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    • 2022
  • Fast Fourier transform (FFT)-based parallel acquisition techniques with reduced computational complexity have been widely used for the acquisition of binary phase shift keying (BPSK) global positioning system (GPS) signals. In this paper, we propose a low computational FFT-based fine acquisition technique, for binary offset carrier (BOC) modulated BPSK signals, that depending on the subcarrier-to-code chip rate ratio (SCR) selectively utilizes the computationally efficient frequency-domain realization of the BPSK-like technique and two-dimensional compressed correlator (BOC-TDCC) technique in the first stage in order to achieve a fast coarse acquisition and accomplishes a fine acquisition in the second stage. It is analyzed and demonstrated that the proposed technique requires much smaller mean fine acquisition computation (MFAC) than the conventional FFT-based BOC acquisition techniques. The proposed technique is one of the first techniques that achieves a fast FFT-based fine acquisition of BOC signals with a slight loss of detection probability. Therefore, the proposed technique is beneficial for the receivers to make a quick position fix when there are plenty of strong (i.e., line-of-sight) GNSS satellites to be searched.

Design of VCO(Voltage Controlled Oscillator) for mobile communication with a built-in voltage regulator (전압 레귤레이터를 내장한 이동통신용 VCO(Voltage Controlled Oscillator) 설계)

  • Cho, Hyon-mook
    • The Journal of the Acoustical Society of Korea
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    • v.16 no.4
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    • pp.76-84
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    • 1997
  • In this paper, one of the core components of a mobile communication system, VCO(Voltage Controlled Oscillator) IC is designed. The VCO IC was designed, have realized as LC turned oscillator using varicap. LC sinusoidal tuned oscillator generally requires external inductors and thus remainding circuit is implemneted in monolithic IC. The circuit is fabricated using an 15 mask IC process and has a die size of 1150um${\times}$780um. The tests showed that VCO was operated at frequencies in the regions between 880MHz-915MHz in the control voltage range of 1V to 3V at 5V supply voltage and as the power supply was varied from 4.5V to 5.5V, the frequency varied 425KHz/V. The VCO IC has frequency shift of 1.97MHz/T, carrier level of -7dBm and power consumption of 16.7mA. Also it has phase noise of -80dBc/Hz, offset at 50KHz and harmonic response of center frequency is -41dBm. For the future development of the transceiver 1 chip, the previously mentioned external devices need to be incorporated into Si MMIC.

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Design and Fabrication of the Push-push Dielectric Resonator Oscillator using a LTCC (LTCC를 이용한 push-push 유전체 공진 발진기의 설계 및 제작)

  • Ryu, Keun-Kwan;Oh, Eel-Deok;Kim, Sung-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.3
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    • pp.541-546
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    • 2010
  • The push-push DRO(dielectric resonator oscillator) using a multi-layer structure of LTCC(low temperature co-fired ceramic) fabrication is designed. After the single DRO of series feedback type in the center frequency of 8GHz is designed, the push-push DRO in the center frequency of 16GHz including the Wilkinson power combiner is designed. The bias circuit affecting the size of oscillator are embedded in the intermediate layer of the LTCC multi-layer substrate. As a result, the large reduction in the size of VCO is obtained compared to the general oscillator on the single layer substrate. Experimental results show that the fundamental and third harmonics suppression are above 15dBc and 25dBc, respectively, and phase noise characteristics of the push-push DRO presents performance of -102dBc/Hz@100KHz and -128dBc/Hz@1MHz offset frequencies from carrier.

Performance Analysis of RF Transformation in DS/CDMA Receiver (DS/CDMA수신기에서 RF변환부의 성능분석)

  • Pyeon, Suk-Bum;Ju, Jae-Han
    • Journal of the Korean Institute of Telematics and Electronics T
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    • v.35T no.2
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    • pp.86-92
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    • 1998
  • In this paper, it is derived the system design parameters for the J-STD-018 of the PCS mobile station(MS) minimum performance using DS/CDMA analyzed the system performance due to the receiver components. The simulation shows the selectivity is -70.96dB at 1.25MHz frequency offset from the carrier frequency while the MS noise figure to satisfy J-STD-018 is 10dB and the input 3rd harmonics intercept point of the MS class I and MS class II-V is -9.5dBm and -14dBm respectively. When the interference power level at the receiver is small, the receiver has better performance as we increase the gain of LNA. However, when the interference level at the receiver is large, the receiver performance is decreased by the effect of the spurious. Thus, the effectiveness of LNA On/Off switching technique is proved as to reduce the effect of the spurious.

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Design of Time Synchronizer for Advanced LR-WPAN Systems (개선된 LR-WPAN 시스템을 위한 시간 동기부 설계)

  • Park, Mincheol;Lee, Dongchan;Jang, Soohyun;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.18 no.5
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    • pp.476-482
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    • 2014
  • Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. IEEE 802.15.4 LR-WPAN system using 2.45 GHz frequency band is very popular for the sensor applications. However, since LR-WPAN only supports the data rate of 250 kbps, it has a limit to be applied to various sensor networks. Therefore, we define the preamble structure which can support the data rates of 31.25 kbps, 62.5 kbps, 125 kbps, and present the low-complexity hardware architecture for time synchronizer based on double-correlation algorithm which can resist the CFO (carrier frequency offset). Implementation results show that the proposed time synchronizer include the logic slice of 18.36 K and four DSP48s, which are reduced at the rate of 79.1% and 99.4%, respectively, compared with existing architecture.