• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 E
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• pp.2186-2188
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• 1999

A high frequency and energy density pulse transformer is a critical component of a high voltage power supply in a traveling wave tube (TWT) amplifier system. In this paper, processes of design, manufacturing, and test of the transformer are discussed. Primary voltage of the transformer is 240 V. The transformer secondary have two outputs which are 4100 V (Helix) and 2050 V (Collector). Total output power is 860 W. Normal operating frequency of the transformer is 10 kHz. In high energy density pulse transformers, temperature rise is a main problem during its operation. From our study, it was found that resonant current due to leakage inductance and stray capacitance was the main cause of temperature rise. This happens because of the inherently high turn-ratio in high voltage transformers. Solutions to reduce stray components are presented.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전력기술부문
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• pp.217-219
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• 2004

The second harmonic component could be decreased by magnetizing inrush when there have been changes to the material of the iron core or its design methodology. The higher the capacitance of the high voltage status and underground distribution, the more the differential current includes the second harmonic during the occurrence of an internal fault. Therefore, the conventional second harmonic-restrained RDR needs modification. This paper describes an advanced numerical algorithm that utilizes terminal voltage, differential current harmonics, harmonic ratio, and flux-differential current slope. Based on the results of testing with WatATP99 simulation data, the proposed algorithm was proven to be faster and more reliable.

• 한국자기학회지
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• 제12권5호
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• pp.168-173
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• 2002

본 연구에서는 인체모델(humman body model; HBM)을 터널링 자기저항(tunneling magneto resistance; TMR)소자에 연결하여 정전기에 대한 방전특성을 연구하였다. 이를 위해 제조된 TMR 시편을 전기적 등가회로 바꿔 HBM에 연결하여 PSPICE를 이용해 시뮬레이션 하였다. 이러한 등가회로에서 접합부분의 모델링 요소들의 값을 변화시켜 방전특성을 관찰할 수 있었다. 그 결과 시편의 저항과 정전용량 성분의 값이 다른 요소들에 비해 수배에서 수백 배까지 커서 정전기 방전(electrostatic discharge; ESD) 민감도를 좌우하는 주요한 요소임을 알 수 있었다. 여기에서 ESD현상에 대한 내구성을 향상시키기 위해서는 정전용량을 증가시키는 것 보다 접합면과 도선의 저항값을 줄이는 것이 유리하다. 그리고 직류 전압에 대해 절연층의 전위 장벽이 낮아져 많은 전류가 흐르게 되는 항복(breakdown)전압과 셀의 물리적 구조 및 성질이 변형되어 회복되지 못하는 파괴(failure)전압을 측정하여 DC 상태에서의 내구성을 연구하였다. 이 결과를 HBM 전압에 대한 파괴 전압으로 간주하여 TMR 소자가 견딜 수 있는 HBM 전압을 예측할 수 있었다.

• The Korean Journal of Physiology and Pharmacology
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• 제3권5호
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• pp.471-479
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• 1999

The Kv channel activity in vascular smooth muscle cell plays an important role in the regulation of membrane potential and blood vessel tone. It was postulated that increased blood vessel tone in hypertension was associated with alteration of Kv channel and membrane potential. Therefore, using whole cell mode of patch-clamp technique, the membrane potential and the 4-AP-sensitive Kv current in cerebral arterial smooth muscle cells were compared between normotensive rat and one-kidney, one-clip Goldblatt hypertensive rat (lK,lC-GBH rat). Cell capacitance of hypertensive rat was similar to that of normotensive rat. Cell capacitance of normotensive rat and 1K,lC-GBH rat were $20.8{\pm}2.3$ and $19.5{\pm}1.4$ pF, respectively. The resting membrane potentials measured in current clamp mode from normotensive rat and 1K,lC-GBH rat were $-45.9{\pm}1.7$ and $-38.5{\pm}1.6$ mV, respectively. 4-AP (5 mM) caused the resting membrane potential hypopolarize but charybdotoxin $(0.1\;{\mu}M)$ did not cause any change of membrane potential. Component of 4-AP-sensitive Kv current was smaller in 1K,lC-GBH rat than in normotensive rat. The voltage dependence of steady-state activation and inactivation of Kv channel determined by using double-pulse protocol showed no significant difference. These results suggest that 4-AP-sensitive Kv channels playa major role in the regulation of membrane potential in cerebral arterial smooth muscle cells and alterations of 4-AP-sensitive Kv channels would contribute to hypopolarization of membrane potential in 1K,lC-GBH rat.

• Journal of Power Electronics
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• 제17권4호
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• pp.942-952
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• 2017

Modular multilevel converters (MMCs) have been receiving extensive research interest in high/medium-voltage applications due to its modularity, scalability, reliability, high-voltage capability, and excellent harmonic performance. Submodule capacitors are usually rather bulky because they have to withstand fundamental frequency voltage fluctuations. To reduce the capacitance of these capacitors, this study proposes a modified MMC with an active power decoupling circuit within each submodule. The modified submodule contains an auxiliary half bridge, with its capacitor split in two. Also, the midpoints of the half bridge and the split capacitors are connected by an inductor. With this modified submodule, the fundamental frequency voltage fluctuation can be suppressed to a great extent. The second-order voltage fluctuation, which is the second most significant component in submodule voltage fluctuations, is removed by the proper control of the second-order circulating current. Consequently, the submodule capacitance is significantly reduced. The viability and effectiveness of the proposed new MMC are confirmed by the simulation and experimental results. The proposed MMC is best suited for medium-voltage applications where power density is given a high priority.

• 센서학회지
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• 제30권6호
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• pp.436-440
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• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

• Tribology and Lubricants
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• 제40권4호
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• pp.111-117
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• 2024

Due to global CO₂ emission reductions and fuel efficiency regulations, the trend toward transitioning from internal combustion engine vehicles to electric vehicles (EVs) has accelerated. Consequently, the problem of EV failures has become a focal point of active research. The parasitic capacitance generated during motor-shaft rotation induces voltage that deteriorates the raceway and ball surfaces of bearings, causing electrical damage in EVs. Despite numerous attempts to address this issue, most studies have been conducted under high viscosity lubricant and low load conditions. However, due to factors such as high-speed operation, rapid acceleration and deceleration, motor heating, and motor system-decelerator integration, current EV applications have shown diminished stability in lubrication films of motor bearings, thereby leveraging the investigation to address the risk of electrical damage. This study investigates the electrical damage to rolling bearing elements in EV motor drive systems. The experimental analysis focuses on the effects of electric currents and operational loads on bearing integrity. A test rig is designed to generate high-rate voltage specific to a motor system's parasitic capacitance, and bearing samples are exposed to these currents for specified durations. Component evaluation involves visual inspections and vibration measurements. In addition, a predictive model for electrical failure is developed based on accumulated data, which demonstrates the ability to predict the likelihood of electrical failure relative to the duration and intensity of current exposure. This in turn reduces uncertainties in practical applications regarding electrical erosion modes.

• 한국전기전자재료학회논문지
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• 제31권5호
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• pp.307-312
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• 2018

Liquid phases in ZnO varistors cause more complex phase development and microstructure, which makes the control of electrical properties and reliability more difficult. Therefore, we have investigated 2 mol% $CaCO_3$ doped $ZnO-Co_3O_4-Cr_2O_3-La_2O_3$ (ZCCLCa) bulk ceramics as one of the compositions without liquid phase sintering additive. The results were as follows: when $CaCO_3$ is added to ZCCLCa ($644{\Omega}cm$) acting as a simple ohmic resistor, CaO does not form a secondary phase with ZnO but is mostly distributed in the grain boundary and has excellent varistor characteristics (high nonlinear coefficient ${\alpha}=78$, low leakage current of $0.06{\mu}A/cm^2$, and high insulation resistance of $1{\times}10^{11}{\Omega}cm$). The main defects $Zn_i^{{\cdot}{\cdot}}$ (AS: 0.16 eV, IS & MS: 0.20 eV) and $V_o^{\bullet}$ (AS: 0.29 eV, IS & MS: 0.37 eV) were found, and the grain boundaries had 1.1 eV with electrically single grain boundary. The resistance of each defect and grain boundary decreases exponentially with increasing the measurement temperature. However, the capacitance (0.2 nF) of the grain boundary was ~1/10 lower than that of the two defects (~3.8 nF, ~2.2 nF) and showed a tendency to decrease as the measurement temperature increased. Therefore, ZCCLCa varistors have high sintering temperature of $1,200^{\circ}C$ due to lack of liquid phase additives, but excellent varistor characteristics are exhibited, which means ZCCLCa is a good candidate for realizing chip type or disc type commercial varistor products with excellent performance.

• 전력전자학회논문지
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• 제25권2호
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• pp.73-78
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• 2020

In this study, a novel reactive power control scheme is proposed to supply stable reactive power to the distribution line by compensating a ripple voltage of DC link. In a single-phase system, a magnitude of second harmonic is inevitably generated in the DC link voltage, and this phenomenon is further increased when the capacity of DC link capacitor decreases. Reactive power control was performed by controlling the d-axis current in the virtual synchronous reference frame, and the voltage control for maintaining the DC link voltage was implemented through the q-axis current control. The proposed method for compensating the ripple voltage was classified into three parts, which consist of the extraction unit of DC link voltage, high pass filter (HPF), and time delay unit. HPF removes an offset component of DC link voltage extracted from integral, and a time delay unit compensates the phase leading effect due to the HPF. The compensated DC voltage is used as feedback component of voltage control loop to supply stable reactive power. The performance of the proposed algorithm was verified through simulation and experiments. At DC link capacitance of 375 uF, the magnitude of ripple voltage decreased to 8 Vpp from 74 Vpp in the voltage control loop, and the total harmonic distortion of the current was improved.

• Journal of Power Electronics
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• 제19권4호
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• pp.881-893
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• 2019

This paper proposes a practical sliding-mode controller design for shaping the impedances of cascaded boost-converter power decoupling circuits for reducing the second order harmonic ripple in photovoltaic (PV) current. The cascaded double-boost converter, when used as power decoupling circuit, has some advantages in terms of a high step-up voltage-ratio, a small number of switches and a better efficiency when compared to conventional topologies. From these features, it can be seen that this topology is suitable for residential (PV) rooftop systems. However, a robust controller design capable of rejecting double frequency inverter ripple from passing to the (PV) source is a challenge. The design constraints are related to the principle of the impedance-shaping technique to maximize the output impedance of the input-side boost converter, to block the double frequency PV current ripple component, and to prevent it from passing to the source without degrading the system dynamic responses. The design has a small recovery time in the presence of transients with a low overshoot or undershoot. Moreover, the proposed controller ensures that the ripple component swings freely within a voltage-gap between the (PV) and the DC-link voltages by the small capacitance of the auxiliary DC-link for electrolytic-capacitor elimination. The second boost controls the main DC-link voltage tightly within a satisfactory ripple range. The inverter controller performs maximum power point tracking (MPPT) for the input voltage source using ripple correlation control (RCC). The robustness of the proposed control was verified by varying system parameters under different load conditions. Finally, the proposed controller was verified by simulation and experimental results.