• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.1
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• Advances in nano research
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• v.3 no.1
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1919-1921
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• 2002

In this paper, we were designed the ferroelectric phase shifter using 3-dB, $90^{\circ}$ branch-line hybrid coupler with two ports terminated in symmetric phase-controllable reflective networks. The design of phase shifter is based on reflection theory of terminating circuits. In order to find the optimum conditions of reflect phase, the effect of a change of capacitance and transmission line connected with two coupled ports of a coupler have been investigated. To obtain more accurate design parameters, finite element method is applied. We were showed large phase variation with small capacitance variation in the parallel connection of capacitor and transmission line by using EM-simulation and circuit-simulation.

• Journal of Mechanical Science and Technology
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• v.15 no.9
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• pp.1268-1273
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• 2001

To successfully establish the ELID-grinding, it is important to properly select the electrolytic condition according to grinding conditions. Currently, the selection of electrolytic condition is mainly dependent on the operators experience, which is one of difficulties preventing the successful application of ELID technique. In this study, an in-process measurement system of the insulating layer using two gap sensors-a capacitance type and an eddy current type-are developed and the change of the thickness of insulating layer during ELID grinding is detected. Evaluation experiments show the possibility to control the electrolytic condition through the in-process measurement of the layer status.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.2-67.2
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• 2012

Graphene is expected to have a significant impact in various fields in the foreseeable future. For example, graphene is considered to be a promising candidate to replace indium tin oxide (ITO) as transparent conductive electrodes in optoelectronics applications. We report the tunability of the wavelength of localized surface plasmon resonance by varying the distance between graphene and Au nanoparticles [1]. It is estimated that every nanometer of change in the distance between graphene and the nanoparticles corresponds to a resonance wavelength shift of ~12 nm. The nanoparticle-graphene separation changes the coupling strength of the electromagnetic field of the excited plasmons in the nanoparticles and the antiparallel image dipoles in graphene. We also show a hysteresis in the conductance and capacitance can serve as a platform for graphene memory devices. We report the hysteresis in capacitance-voltage measurements on top gated bilayer graphene which provide a direct experimental evidence of the existence of charge traps as the cause for the hysteresis [2]. By applying a back gate bias to tune the Fermi level, an opposite sequence of switching with the different charge carriers, holes and electrons, is found [3]. The charging and discharging effect is proposed to explain this ambipolar bistable hysteretic switching.

• Journal of electromagnetic engineering and science
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• v.17 no.1
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• pp.34-38
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• 2017

In this paper, we propose an active tunable bandpass filter (BPF) for efficient spectrum sensing in the TV White Space (TVWS) band. By designing a narrow bandwidth, it is possible to improve the sensing probability. The basic circuit configuration involves switching the PIN diode compromising capacitor bank to change the capacitance of the LC resonant circuit. To cover the whole TVWS band effectively, we add a varactor diode, and the bandwidth is set to 25-MHz. We improve the insertion loss by using the active capacitance circuit. The tunable BPF in the TVWS band with a 20-MHz interval is designed to have 11 channels with a bandwidth of 25 MHz and a low insertion loss of 1.7-2.0 dB.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.211-214
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• 1998

The composite of polyvinylalcohol(PVA) and lithium salts(LiBF$_4$) is prepared for a solid-state electrolyte of electric double layer capacitor. The composite shows a good ionic conductivity. The solid-state electric double layer capacitor is made of PVA-LiBF$_4$ composite, activated carbon and etc.. As evaluation of characteristics of capacitor, capacitance change which measured by charge-discharge test with 2.2V~0V at 8$0^{\circ}C$ for 800 hours, was about 10%. The gravimetric and volumetric capacitance were 10.0 F/g~30.0 F/g and 16.0F/㎤~F/㎤, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.320-323
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• 2000

In the resent years, the Thin Film Transistor Liquid Crystal Display(TFT-LCD) have trend toward larger panel sizes and higher spatial and/or gray-scale resolution. In this trend, Because of its low field effect mobility, a-Si TFT is change to poly-Si TFT. In this paper, both effective-medium model of poly-Si TFTs and empirical capacitance model are applied to Pixel Design Array Simulation Tool (PDAST) and the pixel characteristics of TFT-LCD array were simulated, which were compared with the results calculated by Aim-Spice.

• Journal of the Korean Physical Society
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• v.73 no.10
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• pp.1561-1565
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• 2018

The dielectric properties of the uniaxial relaxor ferroelectric $Sr_xBa_{1-x}Nb_2O_6$ with x = 0.75 were investigated along the polar [001] direction as a function of temperature. The capacitance maximum showed the frequency dispersion commonly observed in relaxors. Additional weak dielectric anomalies were observed in the paraelectric phase; they were only seen during the heating process and disappeared upon subsequent cooling. These were attributed to the existence of large polar clusters strongly pinned at defects and/or to random fields and their metastable characters. Aligning the ferroelectric domains along the polar axis at room temperature removed the high-temperature dielectric anomalies. The dependences of the capacitance and the dielectric maximum temperature on the magnitude of the poling field were investigated.

• Bulletin of the Korean Chemical Society
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• v.32 no.4
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• pp.1298-1302
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• 2011

This study describes the development of an electrochemical array immunochip for the detection of IgG. Interdigitated immunochip platforms were fabricated by sputtering gold on a glass wafer by using MEMS process and then were coated with Eudragit S100, an enteric polymer, forming an insulating layer over the working area of immunochips. The breakdown of the polymer layer was exemplified by the catalytic action of urease which, in the presence of urea, caused an alkaline pH change. This subsequently caused an increase of the double layer capacitance of the underlying electrode. Used in conjunction with a competitive immunoassay format, this allowed the ratio of initial to final electrode capacitance to be directly linked with the concentration of analyte, i.e. IgG. Responses to IgG could be detected at IgG concentration as low as $250\;ngmL^{-1}$ and showed good linearity up to IgG concentration as high as $20\;{\mu}gmL^{-1}$.