• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.599-605
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• 2003

A dual-mode asymmetric canonical filter is widely used in an input demultiplexer for satellite transponder. This paper deals with a simple synthesis method fur an asymmetric canonical filter. The coupling matrix of an asymmetric canonical filter is obtained by applying plane rotation technique to the coupling matrix of a symmetric canonical filter. This paper gives a list of pivots and rotation angles to obtain the coupling matrix of asymmetric canonical structure filters. The coupling matrix of 8th and 10th order asymmetric canonical filter is obtained by this proposed method. It is shown that the frequency response of asymmetric canonical filter is identical to that of symmetric canonical filter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.3
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• pp.278-283
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• 2004

Due to the complex arrangement of frequency plans and spatial overages in modern satellite communications, channels that are non-contiguous in frequency may be amplified by a single power amplifier and transmitted to the ground through one beam. In this paper, a dual-mode canonical filter with dual-passband is presented. The filter adopts dual-mode technique for mass and volume reduction. Canonical structure is adopted for maximum transmission zero realization. To validate the design technique, a 6-pole dual-mode canonical dual-passband filter for Ka-band(30/20 ㎓) satellite transponder is realized. The measured frequency response of the filter shows good agreement with the computed one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12A
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• pp.1346-1353
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• 2007

In this paper, the methods are presented for the calculation of general coupling coefficient matrixes used in the band pass filter design. They are calculated from transmission coefficient($S_{21}$) and reflection coefficient($S_{11}$) with desired characteristics derived from the poles of filter function and return loss(RL). The calculated matrixes from this method are transformed to the folded canonical filter structure using similarity transformation which lends us the practical filter design. Based on the resulting matrix, the folded canonical filter has been designed.

• International Journal of Control, Automation, and Systems
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• v.6 no.1
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• pp.142-148
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• 2008

In this paper, we deal with the problem of reducing the order of the detection filter for the linear time-invariant system. Even if the detection filter is generally designed in the form of full order linear observer, we show that it is possible to reduce its order when the response of fault signals is limited to a subspace of the estimation state space. We propose a method to extract the subspace using the observer canonical form considering the dynamics related to the remaining subspace acts as a disturbance. We designed a reduced order detection filter to reject the disturbance as well as to guarantee fault detection and isolation. A simulation result for a 5th order system is presented as an illustrative example of the proposed design method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.324-329
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• 2002

In the high-speed/low-power digital filter applications like wireless communication systems, canonical signed digit(CSD) linear phase finite impulse response(FIR) filter structures are widely investigated. In this paper, we propose a high-speed/low-power CSD linear phase FIR filter structure using vertical common sub-expression. In the conventional linear phase CSD filter, horizontal common sub-expressions are utilized due to the inherent horizontal common sub-expression of symmetrical filter coefficients. We use the fact that their MSBs are also equal since adjacent filter coefficients have similar values in the linear phase filter Through the examples, it is shown that our proposed structure is more efficient in case that precision of implementation is lower, and tap length are longer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.262-264
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• 2005

We propose a filter design method to suppress the effect of gyroscope mixed random errors at INS system level. It is based on the result that mixed random errors can be represented by a single equivalent ARMA model. At first step, the time difference of equivalent ARMA process is performed, which consider the characteristic of indirect feedback Kalman filter used in INS filter. Next, a state space conversion of time differenced ARMA model is achieved. If the order of AR is greater than that of MA, the controllable or observable canonical form is used. Otherwise, we introduce the state equation of which the state variable is composed of the ARMA model output and several step ahead predicts of that. At final step, a complete form state equation is presented. The simulation results shows that the proposed method gives less transient error and better convergence compared to the conventional filter which assume the mixed random errors as white noise.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.511-512
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• 2006

Three stage(CIC-FIR-FIR) decimation filter in delta-sigma A/D converter for audio is designed. A canonical signed digit(CSD) code method is used to minimize area of multipliers. This filter is designed in 0.25um CMOS process and incorporates $1.36\;mm^2$ of active area. Measured results show that this decimation filter is suitable for digital audio A/D converters.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.391-392
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• 2014

본 논문에서는 Active Power Filter (APF)에서 고조파 전류 보상을 위해 널리 사용되는 Repetitive 제어기의 구현방식을 비교한다. 샘플링 주파수가 높을수록 고조파 보상능력이 증가되는데 기존 Repetitive 제어 방식을 디지털 Canonical 형태로 표현하게 되면 낮은 샘플링 주파수를 가지는 시스템에서는 문제가 없으나 샘플링 주파수가 높은 경우에는 계산시간이 줄어들어 제어기가 정상동작을 하지 않게 된다. 따라서 본 논문에서는 높은 샘플링 주파수에서도 제어기 동작이 가능한 디지털 Repetitive 제어기 구현에 대해 제안하고 5kW Active Power Filter 시제품을 통해 제안한 방식의 우수성을 검증하였다.