• Title/Summary/Keyword: Calculation Time Delay

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A New Predictive Current Controller for a PMSM with consideration of calculation delay

  • Moon H.T.;Youn M.J.
    • Proceedings of the KIPE Conference
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    • 2001.10a
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    • pp.336-340
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    • 2001
  • In a digital system, there are inevitable delays in calculations and applying the inverter output voltages to the motor terminals. Because of the delays, the conventional predictive current controller implemented in the digital system has large overshoot and large harmonics. A new predictive current controller, considering the delays, for a permanent magnet synchronous motor (PMSM) is presented. The effectiveness and feasibilities are shown by experimental results.

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Design of the Single Chip Trigonometric Function Generator with ROMs (ROM을 이용한 SINGLE CHIP SINE FUNCTION GENERATOR의 설계)

  • Hong, Ki-Sang;Hwang, Ho-Jung
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1485-1487
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    • 1987
  • To improve time delay produced in computation of trigonometric function by software method, the function generator was designed to compute the sine function with ROMs. Since the computation speed of trigonometric function can be improved by this ROM, it will be used in various parts required to scientific calculation-radar, FFT and signal processing etc.

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Precursor Discharge Mechanism under EHV in $SF_6$ Gas (초고압 $SF_6$가스중의 선구방전기구)

  • Lee, H.H.;Borin, V.N.;Varivodov, V.N.
    • Proceedings of the KIEE Conference
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    • 1996.07c
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    • pp.1807-1809
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    • 1996
  • The axial discharge at switching operations of EHV $SF_6$ disconnector can lead to the breakdown to the enclosure. Precursor in periphery zone leads to formation of leader over some time delay. Injected charge value depends on electric field and gap geometry. The calculation method for parameters of $SF_6$ insulation for DS in EHV-GIS is suggested by using the new criterion of leader inception in connection with periphery field nearby the boundary of streamer zone.

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Determination Method of Signal Timing Plan Using Travel Time Data (통행시간 자료를 이용한 신호시간계획의 결정 방법)

  • Jeong, Young-Je
    • The Journal of the Korea Contents Association
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    • v.18 no.3
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    • pp.52-61
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    • 2018
  • This research suggested the traffic signal timing calculation model for signal intersections based on sectional travel time. A detection system that collects sectional travel time data such as Urban Transport Information System(UTIS) is applied. This research developed the model to calculate saturation flow rate and demand volume from travel time information using a deterministic delay model. Moreover, this model could determine the traffic signal timings to minimize a delay based on Webster model using traffic demand volume. In micro simulation analysis using VISSIM and its API ComInterface, it checked the saturation conditions and determined the traffic signal timings to minimize the intersection delay. Recently, sectional vehicle detection systems are being installed in various projects, such as Urban Transportation Information System(UTIS) and Advanced Transportation Management System(ATMS) in Korea. This research has important contribution to apply the traffic information system to traffic signal operation sector.

A Study on the Method of Gain Setting of Digital Governor by Dynamic Calculation for Marine Prime Movers (선박 주기관 디지털 거버너의 동적 게인 설정법에 관한 연구)

  • 강인철;최순만;최재성
    • Proceedings of the Korean Society of Marine Engineers Conference
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    • 2002.05a
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    • pp.251-259
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    • 2002
  • The design concept of diesel engines for sea-going ships has been directed to Low-speed/Long-Stroke type to improve the efficiencies of combustion and propelling. But the time-delay property inevitable at such low speed engines gives much difficulties for governors to control the engine speed because they would be apt to go into unstable region especially when operating at low speed. The purpose of this paper is to study the problem of how the governor gain can be calculated dynamically in accordance with the variance of engine speed at least for an engine to be stable. In this study, the property of diesel engine was described as composed of combustion element including dead time and rotating element, and the ultimate gain for the speed control system to be located on the condition of stability limit was proposed based on the frequency characteristics. And the target gains with optimized stability also were proposed by giving proper margin to these ultimate conditions. The results were applied to a model system and the availability was confirmed to be satisfactory.

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A Study On the Gain Setting of a Digital Governor for Marine Diesel Engines by Dynamic Calculation (선박 주기관 디지털 거버너의 동적 이득 설정에 관한 연구)

  • 강인철;최순만;최재성
    • Journal of Advanced Marine Engineering and Technology
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    • v.26 no.5
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    • pp.565-572
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    • 2002
  • The design concept of diesel engines for sea-going ships has been directed to Low-speed/Long-Stroke type to improve the efficiencies of combustion and propelling. But time-delay inevitable at low speed gives much difficulties for governors to control the engine speed because they would be apt to go into unstable region especially when operating at low speed. The purpose of this paper is to study the problem of how the governor gain can be calculated dynamically in accordance with the valiance of engine speed to locate the engine still on the properly stable condition. In this study, the property of diesel engine was described as composed of combustion element including dead time and rotating element, and the ultimate gain for the speed control system to be located on the condition of stability limit was proposed based on the frequency characteristics. And the target gains with optimized stability also were proposed by giving proper margin to these ultimate conditions. The results were applied to a model system and the availability was confirmed to be satisfactory.

A Compensation Method for Time Dealy of Full Digital Synchronous Frame Current Regulator of PWM ac Drives (디지털 동기좌표계 전류제어기에서의 시지연을 고려한 PWM 기법)

  • Bae, Bon-Ho;Sul, Seung-Ki
    • Proceedings of the KIEE Conference
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    • 2001.04a
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    • pp.244-246
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    • 2001
  • In a full digital implementation of a current regulator, the voltage output is inevitably delayed due to arithmetic calculation and PWM. In case of the synchronous frame current regulator, the time delay is accompanied by the rotation of frame. In some applications in which the ratio of sampling frequency to output frequency is not high enough, such as high power drive or super high-speed drive, it is known that the effect of rotation of frame during the delay time causes phase and magnitude error in the voltage output. The error degrades the dynamic performance and can bring about the instability of current regulator at high speed. It is also intuitively known that advancing the phase of voltage output can mitigate the instability. In this paper, the instability problems are studied analytically and a compensation method for the error has been proposed. By means of computer simulation and complex root locus analysis, comparative study with conventional methods is carried out and the effectiveness of proposed method is verified.

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A Study on Delay Time and Capacitance Calculation for Interconnection Line in Multi-Dielectric Layer (다층 유전체에서의 Interconnection Line에 대한 커패시턴스와 지연시간 계산 방법에 관한 연구)

  • 김한구;곽계달
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.9
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    • pp.46-55
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    • 1992
  • This paper propose how to calculate the capacitance for VLSI interconnection lines in multi-dielectric layer. The proposed method is a expansive form of 3-dimensional direct intergral method developed in single-dielectric layer. We took into consideration the effect of multi-dielectric layer by using additional boundary condition instead of modified Green's function. It is used the potential equations in line surface and the electric field equations in dielectric interface as the boundary condition. RC delay time for interconnection line of multi-dielectric layer is obtained from the calculated capacitance value. At this time, we are used Al and WSiS12T as interconnection materials.

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A New Control Method for a Single-Phase Hybrid Active Power Filter based on a Rotating Reference Frame

  • Kim, Jin-Sun;Kim, Young-Seok
    • Journal of Power Electronics
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    • v.9 no.5
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    • pp.718-725
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    • 2009
  • To get instantaneous reference data in a single power system with vector space phasors, the instantaneous load current is adopted as a phase and another new signal, which is delayed through filtering by the phase-delay property of a low-pass filter, is used as the secondary phase. Because the two-phases have a different phase, the instantaneous value of the harmonic current can be obtained without a time-delay in calculation. The reference voltage is created by multiplying the coefficient k by the compensation current using the rotating reference frame synchronized with the source-frequency. To verify the validity of the proposed control method, experiments are carried out on a prototype of the single-phase hybrid active power filter system.

SPICE models of PCB traces in high-speed systems (고속 시스템에서의 PCB 선로의 SPICE 모델)

  • 남상식;손진우;강석열;김석윤
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.1
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    • pp.12-20
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    • 1997
  • Physical interconnect such as Printed Circuit Board(PCB) traces introduces new challenges for parameter extraction and delay calculation for high-speed system design. PCB traces are dominated by frequency dependent LC propagation which makes precharacterization difficult for all possible configurations. Moreover, simulating the transient behavior of the trace for noise and delay analysis requries the combined used of a variety of models and techniques for efficiently handling lossy, low-loss, frequency dependent, and coupled transmission lines together with lumped elements. In this paper we explain how the frequency dependence caused by ground plane proximity and skin effects can be modeled using the adstracted models. These abstracted (lumped) models are SPICE-compatible and can be simulated in time-domain, along with precharacterized lumped parasitic elements and nonlinear driver and load models.

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