• Proceedings of the Korea Contents Association Conference
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• 2004.11a
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• pp.448-452
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• 2004

Cache sensitive $B^+-trees$ with partial keys is cache sensitive tree using both key compression and pointer compression. Although conventional cache sensitive trees consider individuallykey compression and pointer compression, cache sensitive $B^+-trees$ with partial keys make more cache utilization by compressing both key and pointer. We implement bulkload and search algorithms of cache sensitive $B^+-trees$ with partial key. And out performance studies show that cache sensitive $B^+-trees$ with partial key is better than $B^+-trees$ and Simple Prefix $B^+-trees$.

• Journal of KIISE:Databases
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• v.32 no.1
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• pp.12-23
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• 2005

In the past decade, advances in speed of commodity CPUs have iu out-paced advances in memory latency Main-memory access is therefore increasingly a performance bottleneck for many computer applications, including database systems. To reduce memory access latency, cache memory incorporated in the memory subsystem. but cache memories can reduce the memory latency only when the requested data is found in the cache. This mainly depends on the memory access pattern of the application. At this point, previous research has shown that B+ trees perform much faster than T-trees because B+ trees are more cache conscious than T-trees, and also proposed 'Cache Sensitive B+trees' (CSB. trees) that are more cache conscious than B+trees. The goal of this paper is to make T-trees be cache conscious as CSB-trees. We propose a new index structure called a 'Cache Sensitive T-trees (CST-trees)'. We implemented CST-trees and compared performance of CST-trees with performance of other index structures.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10b
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• pp.94-96
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• 2004

기술의 발달로 인하여 컴퓨터에 사용되는 메모리가 대용량화되고, 가격이 저렴해지면서 메인 메모리 데이터베이스 시스템이 주목을 받고 있다. 메인 메모리 데이터베이스 시스템은 디스크 기반 데이터베이스 시스템에 비해 디스크 접근을 줄임으로써, 좀 더 빠른 트랜잭션 처리를 보여주고 있다. 그러나 전원 차단과 같은 장애 발생 시, 메모리의 휘발성으로 인한 데이터 손실에 항상 대비를 해야 한다. 증권, 통신사와 같이 실시간 서비스가 이루어지고, 시스템 장애가 큰 손실로 이어지는 곳에서는 장애 발생 시 데이터의 빠른 복구를 필요로 하게 된다. 본 논문은 메인 메모리 데이터베이스 시스템에서 CST-트리(Cache Sensitive T-tree)보다 좋은 성능을 보이는 CST-트리(Cache Sensitive T-tree)에서 사용할 수 있는 인덱스의 빠른 구축 기법을 제안한다.

• Journal of Korea Multimedia Society
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• v.12 no.10
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• pp.1374-1385
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• 2009

Recently, advances in speed of the CPU have for out-paced advances in memory speed. Main-memory access is increasingly a performance bottleneck for main-memory database systems. To reduce memory access speed, cache memory have incorporated in the memory subsystem. However cache memories can reduce the memory speed only when the requested data is found in the cache. We propose a new cache sensitive T-tree index structure called as $CST^*$-tree for range query search. The $CST^*$-tree reduces the number of cache miss occurrences by loading the reduced internal nodes that do not have index entries. And it supports the sequential access of index entries for range query by connecting adjacent terminal nodes and internal index nodes. For performance evaluation, we have developed a cost model, and compared our $CST^*$-tree with existing CST-tree, that is the conventional cache sensitive T-tree, and $T^*$-tree, that is conventional the range query search T -tree, by using the cost model. The results indicate that cache miss occurrence of $CST^*$-tree is decreased by 20~30% over that of CST-tree in a single value search, and it is decreased by 10~20% over that of $T^*$-tree in a range query search.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1255-1261
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• 2020

Cache side-channel attack is a class of attacks to retrieve sensitive information from a system by exploiting shared cache resources in CPUs. As the attacks are delivered to wide range of environments from mobile systems to cloud systems recently, many detection strategies have been proposed. Since the conventional cache side-channel attacks are likely to incur tremendous number of cache events, most of the previous detection mechanisms were designed to carefully monitor mostly cache events. However, recently proposed attacks tend to incur less cache events during the attack. PRIME+ABORT attack, for example, leverages the Intel TSX instead of accessing cache to measure access time. Because of the characteristic, attack detection mechanisms based on cache events may hardly detect the attack. In this paper, we conduct an in-depth analysis of the PRIME+ABORT attack to identify the other useful hardware events for detection rather than cache events. Based on our finding, we present a novel mechanism called PRIME+ABORT Detector to detect the PRIME+ABORT attack and demonstrate that the detection mechanism can achieve 99.5% success rates with 0.3% performance overhead.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.24-27
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• 2007

주기억 색인 기법인 Tmr-트리가 R-트리에 비해서 삽입시간이 오래 걸린다는 단점이 있다. 본 논문은 L2 캐시를 최대한 활용하여 기존 Tmr-트리의 장점을 가지는 새로운 CSTmr-트리(Cache Sensitive Tmr-트리)구조를 제안하고, 이 구조에 삽입, 삭제 등의 알고리즘을 제안하였다. 제안한 구조와 알고리즘을 다른 인덱스 구조와 비교하여 CSTmr-트리의 우수성을 보인다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1237-1246
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• 2020

Recently, several cache side channel attacks have been proposed to extract secret information by exploiting design flaws of the microarchitecture. The Flush+Reload attack, one of the cache side channel attack, can be applied to malicious application attacks due to its properties of high resolution and low noise. In this paper, we proposed a detection system, which detects the cache-based attacks using the PCM(Performance Counter Monitor) for monitoring CPU cache activity. Especially, we observed the variation of each counter value of PCM in case of two kinds of attacks, Spectre attack and secret recovering attack during AES encryption. As a result, we found that four hardware counters were sensitive to cache side channel attacks. Our detector based on machine learning including SVM(Support Vector Machine), RF(Random Forest) and MLP(Multi Level Perceptron) can detect the cache side channel attacks with high detection accuracy.

• Journal of KIISE:Databases
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• v.30 no.6
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• pp.606-628
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• 2003

Recently, there have been many research efforts reported in the literature that focus on the cache consistency problems of mobile clients resulting from their frequent disconnections with a server in mobile environments. To cope with this problem, a number of methods based on the invalidation report scheme has been proposed. However, these proposed methods are sensitive to the disconnection time of mobile clients and independent of the frequency of data updates in the server. As a result, although the number of data updated in the server is small, the traditional methods can not guarantee the cache consistency of mobile clients if their disconnection time is over the time period the invalidation report is allowed to cover. In this paper, we propose an efficient cache consistency method called CCI(Cost-based Cache Invalidation) for mobile clients that take into account not only the disconnection time but also the frequencies of data updates in the server We also present an in-depth experimental analysis by comparing CCI method with BT(Broadcasting Time stamp) method based on Invalidation Report.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.2
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• pp.66-74
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• 2008

Since modem embedded systems need to access, manipulate or store sensitive information, it requires being equipped with cryptographic file systems. However, cryptographic file systems result in poor performance so that they have not been widely adapted to embedded systems. Most cryptographic file systems degrade the performance unnecessarily because of system architecture. This paper proposes ISEA (Indexed and Separated Encryption Approach) that supports for encryption/decryption in system architecture and removes redundant performance loss. ISEA carries out encryption and decryption at different layers according to page cache layer. Encryption is carried out at lower layer than page cache layer while decryption at upper layer. ISEA stores the decrypted data in page cache so that it can be reused in followed I/O request without decryption. ISEA provides page-indexing which divides page cache into cipher blocks and manages it by a block. It decrypts pages partially so that it can eliminate unnecessary decryption. In synthesized experiment of read/write with various cache hit rates, it gives results suggesting that ISEA has improved the performance of encryption file system efficiently.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.2
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• pp.227-242
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• 2022

This paper presents a Cache-Coherency Interconnect(CCI)-based Android pattern screen lock(PSL) attack on modern ARM processors. CCI has been introduced to maintain the cache coherency between the big core cluster and the little core cluster. That is, CCI is the central interconnect inside SoC that maintains cache coherency and shares data. In this paper, we reveal that CCI can be a side channel in security, that an adversary can observe security-sensitive operations. We design and implement a technique to compromise Android PSL within only a few attempts using the information of CCI in user-level applications on Android Nougat. Further, we analyzed the relationship between the pattern complexity and security. Our evaluation results show that complex and simple patterns would have similar security strengths against the proposed technique.