• 제목/요약/키워드: CMOS voltage reference

Search Result 195, Processing Time 0.031 seconds

Modified Low-Votlage CMOS Bandgap Voltage Reference with CTAT Compensation (개선된 CTAT 보상을 가지는 저전압 CMOS Bandgap Voltage Reference)

  • Kim, Jae-Bung;Cho, Seong-Ik
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.61 no.5
    • /
    • pp.753-756
    • /
    • 2012
  • In this paper, a modified low-votlage CMOS bandgap voltage reference with CTAT compensation is presented. The proposed structure doesn't use PTAT current. The proposed structure is more simple than the existing structure and doesn't use the eighteen BJT. The modified low-votlage CMOS bandgap voltage reference with CTAT compensation has been successfully verified in a standard 0.18um CMOS process. The simulation results have confirmed that, with the minimum supply voltage of 1.25V, the output reference voltage at 549mV has a temperature coefficient of 12$ppm/^{\circ}C$ from $0^{\circ}C$ to $100^{\circ}C$.

The New Design of CMOS Voltage-Current Reference Circuit for Stable Voltage-Current Applications (새로운 CMOS 전압-전류 안정화 회로 설계)

  • Kim, Yeong-Min;Hwang, Jong-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2004.07b
    • /
    • pp.1239-1243
    • /
    • 2004
  • A novel voltage-current reference circuit for stable voltage-current applications is Proposed. Circuits for a positive and for a negative voltage-current reference are presented and are designed with commercial CMOS technology. The voltage-current reference that is stable over ambient temperature variations is an important component of most data acquisition systems. These results are verified by the HSPICE simulation $0.8{\mu}m$ parameter. As the result, the temperature dependency of output voltage and output current each is $0.57mV/^{\circ}C$, $0.11{\mu}A/^{\circ}C$ and the power dissipation is 1.8 mV on 5V supply voltage.

  • PDF

A Design of CMOS VCO Using Bandgap Voltage Reference (밴드갭 기준 전압을 이용한 CMOS 전압 제어 발진기의 설계)

  • 최진호
    • The Transactions of the Korean Institute of Electrical Engineers C
    • /
    • v.52 no.10
    • /
    • pp.425-430
    • /
    • 2003
  • A CMOS Voltage-Controlled Oscillator(VCO) for application at temperature stable system is designed. The VCO consists of bandgap voltage reference circuit, comparator, and voltage-to-current converter and the VCO has a temperature stable characteristics. The difference between simulated and calculated values is less than about 5% in output characteristics when the input voltage range is from 1V to 3.25V. The CMOS VCO has error less than about $\pm$0.85% in the temperature range from $-25^{\circ}C$ to $75^{\circ}C$.

Temperature Stable Current Source Using Simple Self-Bias Circuit

  • Choi, Jin-Ho
    • Journal of information and communication convergence engineering
    • /
    • v.7 no.2
    • /
    • pp.215-218
    • /
    • 2009
  • In this paper, temperature stable current and voltage references using simple CMOS bias circuit are proposed. To obtain temperature stable characteristics of bias circuit a bandgap reference concept is used in a conventional circuit. The parasitic bipolar transistors or MOS transistors having different threshold voltage are required in a bandgap reference. Thereby the chip area increase or the extra CMOS process is required compared to a standard CMOS process. The proposed reference circuit can be integrated on a single chip by a standard CMOS process without the extra CMOS process. From the simulation results, the reference current variation is less than ${\pm}$0.44% over a temperature range from - $20^{\circ}C$ to $80^{\circ}C$. And the voltage variation is from - 0.02% to 0.1%.

On-Chip Full CMOS Current and Voltage References for High-Speed Mixed-Mode Circuits (고속 혼성모드 집적회로를 위한 온-칩 CMOS 전류 및 전압 레퍼런스 회로)

  • Cho, Young-Jae;Bae, Hyun-Hee;Jee, Yong;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SC
    • /
    • v.40 no.3
    • /
    • pp.135-144
    • /
    • 2003
  • This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.

A study on a CMOS analog cell-library design-A CMOS on-chip current reference circuit (CMOS 아날로그 셀 라이브레이 설계에 관한 연구-CMOS 온-칩 전류 레퍼런스 회로)

  • 김민규;이승훈;임신일
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.33A no.4
    • /
    • pp.136-141
    • /
    • 1996
  • In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

  • PDF

CMOS on-chip voltage and current reference circuits for low-voltage applications (저전압용 CMOS 온-칩 기준 전압 및 전류 회로)

  • 김민정;이승훈
    • Journal of the Korean Institute of Telematics and Electronics C
    • /
    • v.34C no.4
    • /
    • pp.1-15
    • /
    • 1997
  • This paper proposes CMOS on-chip voltage and current reference circuits that operate at supply voltages between 2.5V and 5.5V without using a vonventional bandgap voltage structure. The proposed reference circuits based on enhancement-type MOS transistors show low cost, compatibility with other on-chip MOS circuits, low-power consumption, and small-chip size. The prototype was implemented in a 0.6 um n-well single-poly double-metal CMOS process and occupies an active die area of $710 um \times 190 um$. The proposed voltage reference realizes a mean value of 0.97 V with a standard deviation of $\pm0.39 mV$, and a temperature coefficient of $8.2 ppm/^{\circ}C$ over an extended temeprature range from TEX>$-25^{\circ}C$ to $75^{\circ}C$. A measured PSRR (power supply rejection ratio) is about -67 dB at 50kHz.

  • PDF

A Low-Power Current-Mode CMOS Voltage Reference Circuit (저전력 전류모드 CMOS 기준전압 발생 회로)

  • 권덕기;오원석
    • Proceedings of the IEEK Conference
    • /
    • 1998.10a
    • /
    • pp.1077-1080
    • /
    • 1998
  • In this paper, a simple low-power current-mode CMOS wotage reference circuit is proposed. The reference circuit of enhancement-mode MOS transistors and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a threshold voltage. The designed circuit has been simulated using a $0.65\mu\textrm{m}$ n-well CMOS process parameters. The simulation results show that the reference circuit has a temperature coefficient less than $7.8ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.079%/V for a temperature range from $-30^{\circ}C$ to $130^{\circ}C$ and a VDD range from 4.0V to 12V. The power consumption is 105㎼ for VDD=5V and $T=30^{\circ}C.$ The proposed reference circuit can be designed to generate a wide range of reference voltages owing to its current-mode operation.

  • PDF

A Design of CMOS Subbandgap Reference using Pseudo-Resistors (가상저항을 이용한 CMOS Subbandgap 기준전압회로 설계)

  • Lee, Sang-Ju;Lim, Shin-Il
    • Proceedings of the KIEE Conference
    • /
    • 2006.10c
    • /
    • pp.609-611
    • /
    • 2006
  • This paper describes a CMOS sub-bandgap reference using Pseudo-Resistors which can be widely used in flash memory, DRAM, ADC and Power management circuits. Bandgap reference circuit operates weak inversion for reducing power consumption and uses Pseudo-Resistors for reducing the chip area, instead of big resistor. It is implemented in 0.35um Standard 1P4M CMOS process. The temperature coefficient is 5ppm/$^{\circ}C$ from $40^{\circ}C$ to $100^{\circ}C$ and minimum power supply voltage is 1.2V The core area is 1177um${\times}$617um. Total current is below 2.8uA and output voltage is 0.598V at $27^{\circ}C$.

  • PDF

A Low-Power CMOS Current Reference Circuit (저전력 CMOS 기준전류 발생회로)

  • 김유환;권덕기;이종렬;유종근
    • Proceedings of the IEEK Conference
    • /
    • 2001.06b
    • /
    • pp.89-92
    • /
    • 2001
  • In this paper, a simple low-power CMOS current reference circuit is proposed. The reference circuit includes parasitic pnp BJTs and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a base-to-emitter voltage. The designed circuit has been simulated using a 0.25${\mu}{\textrm}{m}$ n-well CMOS process parameters. The simulation results show that the reference current is 34.96$mutextrm{A}$$\pm$0.04$mutextrm{A}$ in the temperature range of -2$0^{\circ}C$ to 12$0^{\circ}C$ The reference current varies less than 0.6% when the power supply voltage changes from 2.5V to 3.5V For $V_{DD=5V}$ and T=3$0^{\circ}C$ the power consumption is 520㎼ during normal operation but reduces to 0.l㎻ during power-down mode.

  • PDF