• Journal of Sensor Science and Technology
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• v.12 no.1
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• pp.51-56
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• 2003

We describe a charge pump circuit using VCO (voltage controlled oscillator) for storing information into local memories in neural networks. The VCO is used for adjusting the output voltage of the charge pump to the reference voltage and for reducing the fluctuation generated by the clocking scheme. The charge pump circuit is simulated by using Hynix 0.35um CMOS process parameters. The proposed charge pump operates properly regardless to the temperature and the supply voltage variation.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.345-348
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• 2000

In this paper, We described the procedures to generate an input-output buffer information specification (IBIS) model in digital IC circuits. We gives the method to describe IBIS standard I/O for the characteristics of I/O buffer and to represent its electrical characteristics. The parameters of I/O structure for I/O buffer modelling are also referred, and an IBIS model for CMOS, TTL IC, ROM and RAM constructed amounts about 216. This IBIS model can be used to the simulation of signal integrity of high speed circuits in a PCB level.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.1-11
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• 2004

A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.519-522
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• 2002

In this paper, we analyze the impact of plasma etching process induced device degradation on low temperature poly-Si TFTs. The results indicate the relationship between device degradation and PPID effect during plasma fabrication. The dual-gate structure, which is used to suppress leakage current, is also discussed in this research.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.48-54
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• 1999

We designed the optimal device parameters of the retrograde well and the gettering layer(buried layer) using the high energy ion implantation for the next generation of CMOS struoture and proposed two models and simulated these models with Athena and Atlas, Silvaco Co. We obtained trigger currents which is more than 600 ${\mu}A/{\mu}m$ when the structure has been combined the gettering layer and the retrograde well. And the second model(twin retrograde well) was obtained that holdingcurrents were over 2500${\mu}A/{\mu}m$. As results, the more heavier dose, the more improved the latch-up immunity. The n'-p' spacing was fixed a 2${\mu}m$ in both models.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2000.05a
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• pp.125-134
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• 2000

In this paper, we proposed a new circuit construction method that reduced the number of CMOS devices of singleton fuzzy controller(SFC) through the proposing a new membership function circuit(MFC) which uses the language variable selecting and the coefficient selecting circuit. According to the range of input values, we can choose the language variables beforehand which will be used in the inference. So we proposed the new MFC which generates the only necessary language variables. Also, we removed all rules of which adapting degree of their antecedents is zero through proposing the coefficient selecting circuit which beforehand selects the coefficients which will influence the inference result. Though this method, we simplified the structure of SFC and reduced the size of hardware. And to solve the problem in the current mode with respect to the restriction of the fan-out number, voltage-input and current-out membership function circuits are constituted of operational transconductance amplifiers. A membership function circuit which includes the language variable selecting circuit, a minimum operation circuit we implemented by current mode CMOS devices. As a result of applying proposed method, total numbers of blocks and devices wave decreased. If the number of variables and antecedents are getting larger, this method is more efficient.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.58-64
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• 2008

A 6Gbps 1:2 demultiplexer(DEMUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. For high speed performance current mode logic(CML) flipflop was used and inductive peaking technology was used so as to obtain higher speed than conventional Current mode logic flipflop. On-chip spiral inductor was designed to maximize the inductive peaking effect using stack structure. Total twelve inductors of $100{\mu}m^2$ area increase was used. The measurement was processed on wafer and 1:2 demultiplexer with and without micro stacked spiral inductors were compared. For 6Gbps data rate measurement, eye width was improved 7.27% and Jitter was improved 43% respectively. Power consumption was 76.8mW and eye height was 180mV at 6 Gbps

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2000.11a
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• pp.357-365
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• 2000

In this paper, we proposed a new circuit construction method that reduced the number of CMOS devices of singleton fuzzy controller(SFC) through the proposing a new membership function circuit(MFC) which uses the language variable selecting and the coefficient selecting circuit. According to the range of input values, we can choose the language variables beforehand which will be used in the inference. So we proposed the new MFC which generates the only necessary language variables. Also, we removed all rules of which adapting degree of their antecedents is zero through proposing the coefficient selecting circuit which beforehand selects the coefficients which will influence the inference result. Though this method, we simplified the structure of SFC and reduced the size of hardware. And to solve the problem in the current mode with respect to the restriction of the fan-out number, voltage-input and current-out membership function circuits are constituted of operational transconductance amplifiers. A membership function circuit which includes the language variable selecting circuit, a minimum operation circuit we implemented by current mode CMOS devices. As a result of applying proposed method, total numbers of blocks and devices wave decreased. If the number of variables and antecedents are getting larger, this method is more efficient.