• 전자공학회논문지C
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• 제34C권1호
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• pp.1-11
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• 1997

A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.781-792
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• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.

• 정보처리학회논문지A
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• 제15A권2호
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• pp.69-74
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• 2008

본 논문은 MOS 전류모드 논리회로 (MOS current-mode logic circuit)의 누설전류를 감소시키기 위해 슬립 트랜지스터 (sleep-transistor) 트랜지스터를 이용하여 저 전력 MOS 전류모드 논리회로를 구현하는 새로운 구조를 제안하였다. 슬립 트랜지스터는 누설전류를 최소화하기 위해 고 문턱전압 PMOS 트랜지스터 (high-threshold voltage PMOS transistor)를 사용하였다. $16\;{\times}\;16$ 비트 병렬 곱셈기를 제안한 구조에 적용하여 제안한 구조의 타당성을 입증하였다. 이 회로는 기존 MOS 전류모드 논리회로 구조에 비해 대기전력소모가 1/50으로 감소하였다. 이 회로는 삼성 $0.35\;{\mu}m$ 표준 CMOS 공정을 이용하여 설계하였으며, HSPICE를 이용하여 검증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.146-153
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• 2006

We have been investigating InGaAs HEMTs as a future high-speed and low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the side-recess spacing $(L_{side})$ on the logic performance of 50 nm $In_{0.7}Ga_{0.3}As$ As HEMTs. We have found that $L_{side}$ has a large influence on the electrostatic integrity (or short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance of the device. For our device design, an optimum value of $L_{side}$ of 150 nm is found. 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs with this value of $L_{side}$ exhibit $I_{ON}/I_{OFF}$ ratios in excess of $10^4$, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a $V_{CC}$ of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs with similar gate lengths. Our work confirms that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs FETs hold considerable promise.

• 전기학회논문지
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• 제67권6호
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• pp.745-752
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• 2018

ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.347-350
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• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• 전자공학회논문지
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• 제50권4호
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• pp.65-72
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• 2013

본 논문에서는 멤리스터 기반의 논리 게이트와 멤리스터-CMOS 기반의 프리미티브 IP 설계 방법을 제안하였다. 회로 설계를 위한 멤리스터 모델을 제시하고 멤리스터의 AND 및 OR 연결을 기본으로 멤리스터-CMOS 회로설계를 위한 프리미티브 IP설계 방법을 제안하였고, $0.18{\mu}m$ CMOS 공정과 멤리스터 SPICE 모델을 이용한 시뮬레이션을 통해 검증되었다. 회로는 멤리스터와 CMOS 결합을 하여 레이아웃 설계를 하고 네트리스트를 추출하였다. 디지털 프리미티브 IP들에 대해 기존의 CMOS와 면적비교를 수행하였으며, 멤리스터-CMOS 전가산기는 CMOS 전가산기에 비하여 47.6 %의 면적이 감소되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.70-81
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• 2002

This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pn-junction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and vMOS circuits.

• 전기전자학회논문지
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• 제8권2호
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• pp.161-165
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• 2004

본 논문은 CMOS 에지 완료검출 신호를 이용하여 8bit 웨이브파이프라인 덧셈기를 설게하였다. 이 구조는 클럭이 필요 없이 동작한다. 에지감지후 신호완료를 검출하는 알고리즘회로는 센서회로와 래치로 구성되어있다. 제안하는 구조를 이용하여 8bit 덧셈기의 출력이 거의 같은 시간에 만들어 지도록 정렬된다. 시뮬레이션에서 0.35um CMOS 공정을 사용하여 3.3V 공급전압으로 1GHz 동작을 확인하였다.