• Journal of the Korea Society for Simulation
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• v.17 no.4
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• pp.199-208
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• 2008

Lately, since Complementary Metal Oxide Semiconductor(CMOS) image sensor system has low power, low cost and been miniaturized, hardware and applied software studies using these strengths are being carrying on actively. However, the products equipped with CMOS image sensor based polling method yet has several problems in degree of completeness of applied software and firmware, compared with hardware’s. CMOS image sensor system has an ineffective synchronous problem due to superfluous message exchange. Also when a sending of data is delayed continually, overhead of re-sending is large. So because of these, it has a problem in structural stability according to Polling Method. In this study, polling cycle was subdivided in high-speed synchronization method of firmware -based through MCU and synchronization method of Stepwise was proposed. Also, re-connection and data sending were advanced more efficiently by using interrupt way. In conclusion, the proposed method showed more than 20 times better performance in synchronization time and error connection. Also, a board was created by using C328R board of CMOS image sensor-based and ATmega128L which has low power, MCU and camera modules of proposed firmware were compared with provided software and analyzed in synchronization time and error connection.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1235-1242
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• 2008

In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.809-813
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• 2004

In this paper, we developed a network camera for CMOS camera module inspection. The design, implementation details including embedded linux porting and CPLD logics, and performance of network camera are described. The network camera consists of SoC(S3C4530A), CPLD and CMOS image sensor. In order to image data of CMOS image sensor we designed capture logics on CPLD by using VHDL program. Embedded Linux such as uClinux is performed on the network camera to utilize development environment and TCP/IP protocol specification. The application is based on socket communication between GUI on PC and Embedded Linux based network camera. When JPEG compression is applied, the transmission speed was improved enough for this system to be used for an alternative of expensive CCTV or remote monitoring system in a power plant and uninhabited places.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Journal of Sensor Science and Technology
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• v.15 no.5
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• pp.341-346
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• 2006

We have fabricated SOI CMOS active pixel image sensor with the pinned photodiode on handle wafer in order to reduce dark currents and improve spectral response. The structure of the active pixel image sensor is 4 transistors APS which consists of a reset and source follower transistor on seed wafer, and is comprised of the photodiode, transfer gate, and floating diffusion on handle wafer. The source of dark current caused by the interface traps located on the surface of a photodiode is able to be eliminated, as we apply the pinned photodiode. The source of dark currents between shallow trench isolation and the depletion region of a photodiode can be also eliminated by the planner process of the hybrid bulk/SOI structure. The photodiode could be optimized for better spectral response because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. The dark current was about 6 pA at 3.3 V of floating diffusion voltage in the case of transfer gate TX = 0 V and TX=3.3 V, respectively. The spectral response of the pinned photodiode was observed flat in the wavelength range from green to red.

• Journal of Sensor Science and Technology
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• v.26 no.4
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• pp.223-227
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• 2017

Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sensitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during integration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sensitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator determines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A $94{\times}150$ pixel array image sensor was designed using a conventional $0.18{\mu}m$ CMOS process and its performance was simulated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.65-70
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• 2006

An image sensor has limited dynamic range while the human eye has logarithmic response over wide range of light intensity. Although the sensor gain can be set high to identify details in darker area on the image, this results in saturation in brighter area. The gamma correction is essential to fit the human eye response. However, the digital gamma correction degrades image quality especially for darker area on the image due to the limited ADC resolution and the dynamic range. This Paper proposes a CMOS image sensor (CIS) with a nonlinear analog-to-digital converter (AU) which performs analog gamma correction. The CIS with the proposed nonlinear analog-to-digital conversion scheme was fabricated with a $0.35{\mu}m$ CMOS process. The analog gamma correction using the proposed nonlinear ADC CIS provides the 2.2dB peak-signal-to-noise-ratio(PSM) improved image qualify than conventional digital gamma correction. The PSNR of the image obtain from the digital gamma correction is 25.6dB while it is 27.8dB for analog gamma correction. The PSNR improvement over digital gamma correction is about $28.8\%$.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.517-520
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• 2003

Commercial video scope use CCD sensor and frame grabber for image capture and A/D interface but application limited by input resolution and high cost. In this paper we introduce portable video scope using CMOS sensor, USB pen and tuner card (low frame grabber) in place of commercial CCD sensor and frame grabber. Our video scope serves as an essential link between advancing commercial technology and research, providing cost effective solutions for educational, engineering and medical applications across an entire spectrum of needs. The software implementation is done using Direct Show in second version after initial trials using First version VFW (video for window), which gave very low frame rate. Our video scope operates on windows 98, ME, XP, 2000. The drawback of our video scope is crossover problem in output images caused due to interpolation, which has to be rectified for more efficient performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.50-57
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• 2008

In this paper, a high-efficiency charge pump for use in CMOS image sensor(CIS) is proposed. The proposed charge pump pursues high pumping efficiency by minimizing the switching and reversion losses by taking advantage of operation characteristics of CIS. That is, the proposed charge pump minimizes the switching loss by dynamically controlling the size of clock driver, pumping capacitor, and charge transfer switch based on the operation phase of CIS pixel sensor. The charge pump also minimizes the reversion loss by guaranteeing a sufficient non-overlapping period of local clocks using a tri-state local clock driver adapting the schmitt trigger. Comparison results using a 0.13-um CMOS process technology indicate that the proposed charge pump achieves up to 49.1% reduction on power consumption under no loading current condition as compared to conventional charge pump. They also indicate that the charge pump provides 19.0% reduction on power consumption under the maximum loading current condition.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.341-344
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• 2002

This paper is proposed a 8-bit analog to digital converter for CMOS image sensor. A analog to digital converter for CMOS image sensor is required function to control gain. Frequency divider is used In control gain in this proposed analog to digital converter. At 3.3 Volt power supply, total static power dissipation is 8㎽ and programmable gain control range is 30㏈. Newly suggested analog to digital converter is designed by 0.35um 2-poly 4-metal CMOS technology.