• 전자공학회논문지A
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• 제31A권3호
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• pp.39-46
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• 1994

CMOS LCD driving circuits using poly-Si TFT have been designed and basic blocks including test patterns have been fabricated. Column driver drives the pixels by block because polu-Si TFT can not operate at the speed of video signal. Row driver has mode selection circuit which can select a mode between interlacing mode and non-interlacing mode. Experimental results show shift register can operate at 1MHz colck frequency with 4pF load.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.629-631
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• 2004

The proposed output buffer is presented for driving large-size LCD panels. This output buffer is designed by adding some simple circuitry to the conventional two-stage operational amplifier. The proposed circuit is simulated in a high-voltage 0.35um CMOS process with HSPICE. The simulated result is more improved settling time than that of conventional one.

• 방사선산업학회지
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• 제6권1호
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권4호
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• pp.269-274
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• 2004

Current delivery system, in which the analog current produced by a unique DAC circuit is stored into a current-memory circuit and delivered in a time-divided sequence, shows variation of output current as low as 4% in a current source data-driver IC for AM-OLED driven by a current-programmed method without any fuse repairing after fabrication. This driver IC has 54 outputs and can sink constant current as low as 3 ${\mu}A$ with 6-bit analog levels. Such a low current level without variation can hardly be obtained by an ordinary MOS transistor because the current level is in the sub-threshold region and changes exponentially with threshold voltage variation. Thus we adopted a current mirror circuit composed of bipolar transistors to supply well-controlled current within a nano-ampere range.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1305-1308
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• 2008

In this study, we redesigned the reliable integrated on-panel display gate driver that was equipped with dual pull-down as well as controlled discharge-path structure to reduce the high voltage stress effect and realized with TSMC 0.35 um CMOS-based technology before. An improved discharge path and a low noise design are proposed for our new a-Si TFT process implementation. Our novel reliable gate driver design can make each cell of shift register to be insensitive to the coupling noise of that stage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.573-574
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• 2008

In this paper, we propose a mixed driving circuit for the source driver of QVGA-scale TFT-LCD driver IC to reduce the area of the source driver. In the mixed driving circuit, graphic data pass or go through the mixed channel driver whether RGB data are the same or not. The mixed driving circuit has been designed in transistor level using the 0.35um CMOS technology and has been verified using Hspice.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.661-662
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• 2006

This paper introduces a CMOS clock driver that shows a high efficiency of electric power (lower power consumption) with the supply of lower voltage(VDD), by taking advantage of charge recycling technology. Comparing with the existing structure, this driver showed the improved maximum efficiency of electric power; 72% and 68%, with the supplied voltage of 1.8v and 1.2v, respectively. Since the output waveform shows the tri-state operating region, utilization is expected in the digital integrated circuits.

• 한국통신학회논문지
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• 제31권3A호
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• pp.356-359
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• 2006

A monolithic SiGe HBT variable gain driver amplifier(VGDA) with high dB-linear gain control and high linearity has been developed as a driver amplifier with ground-shielded microstrip lines for 5-GHz transmitters. The VGDA consists of three blocks such as the cascode gain-control stage, fixed-gain output stage, and voltage control block. The circuit elements were optimized by using the Agilent Technologies' ADSs. The VGDA was implemented in STMicroelectronics' 0.35${\mu}m$ Si-BiCMOS process. The VGDA exhibits a dynamic gain control range of 34 dB with the control voltage range from 0 to 2.3 V in 5.15-5.35 GHz band. At 5.15 GHz, maximum gain and attenuation are 10.5 dB and -23.6 dB, respectively. The amplifier also produces a 1-dB gain-compression output power of -3 dBm and output third-order intercept point of 7.5 dBm. Input/output voltage standing wave ratios of the VGDA keep low and constant despite change in the gain-control voltage.

• 한국정보통신학회논문지
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• 제23권6호
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• pp.719-725
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• 2019

본 연구에서는 2.4-GHz CMOS 전력 증폭기의 저 출력 전력 영역에서의 전력 변환 효율을 개선시키기 위한 이중모드 증폭기 구조를 제안하였다. 이를 위하여 출력 정합 회로 및 발룬의 역할을 하는 출력부 변압기의 1차 측을 두 개로 나누고, 그 중 하나는 전력 증폭단의 출력부와, 나머지 하나는 구동 증폭단의 출력부와 연결 되도록 구성하였다. 이를 통하여, 전력 증폭기가 고 출력 전력 영역에서 동작 할 경우, 일반적인 전력 증폭기 동작과 동일하게 동작 하며, 반대로 전력 증폭기가 저출력 전력 영역에서 동작 할 경우, 전력 증폭단은 작동을 하지 않으며, 구동 증폭단의 출력이 전력 증폭기의 최종 출력부로 전달 되도록 구성하였다. 이 경우, 저출력 전력 영역에서는 전력 증폭단에서의 dc 전력소모가 원천적으로 차단되기 때문에 저출력 전력 영역에서의 전력 변환 효율을 개선시킬 수 있다. 제안하는 구조는 180-nm RFCMOS 공정을 통해 설계된 2.4-GHz 전력 증폭기의 측정을 통하여 그 효용성을 검증하였다.

• 한국전기전자재료학회논문지
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• 제23권8호
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• pp.593-600
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• 2010

In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 ${\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.