• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.589-592
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• 2002

A CMOS power amplifier for IMT-2000 is designed with 0.25-${\mu}m$ CMOS technology. This amplifier circuits consist of two cascode stages. Used cascode structure has good reverse isolation. These amplifier circuits consist of two stages which are driver stage and power amplification stage. The designed power amplifier is simulated with ADS using 0.25-${\mu}m$ CMOS library at 3.3 V power supply. Simulation results indicate that the amplifier has a PAE of 39 % and power gain of 24 dBm at 1.95 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.104-109
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• 2009

At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for complicated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabriccated in a 0.13-$^{\mu}m$ CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. Deemphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 mA for a 400-mV output voltage swing.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1372-1381
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• 2017

This paper presents a high-side switch driver IC capable of improving the current sensing accuracy and providing reverse battery protection. Power semiconductor switches used to replace relay switches are encumbered by two disadvantages: they are prone to current sensing errors and they require additional external protection circuits for reverse battery protection. The proposed IC integrates a gate driver and current sensing blocks, thus compensating for these two disadvantages with a single IC. A p-sub-based 90-V $0.13-{\mu}m$ bipolar-CMOS-DMOS (BCD) process is used for the design and fabrication of the proposed IC. The current sensing accuracy (error ${\leq}{\pm}5%$ in the range of 0.1 A-6.5 A) and the reverse battery protection features of the proposed IC were experimentally tested and verified.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.122-122
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• 2009

최근 PC의 성능이 향상되면서, 고성능의 전원공급 장치가 요구되고 있다. 특히 CPU에 대전력을 공급하는 싱크로너스 벅 컨버터는 파워 MOSFET을 구동하기 위해 별도의 구동 IC가 필요하다. 본 논문은 adaptive 지연을 이용하여 파워 MOSFET을 구동하는 싱크로너스 벅 구동 IC를 설계하였다. 고정밀도의 밴드캡 기준회로와 비교기를 이용하여 30 ns의 adaptive 지연을 생성하며, 전력소모를 줄이기 위해 저전압에서 동작하는 UVLO(under voltage lock out)를 설계하였다. 또한 상단 파워 MOSFET을 구동하기 위하여 부트스트랩 방식을 이용하며, 부트스트랩 다이오드를 IC 내부에 내장하여 컨버터의 설계비용을 줄였다. 설계한 구동 IC의 동작 전압 범위는 8 V - 15 V이며, 출력 전류는 최대 2A이다. 싱크로너스 벅 구동 IC는 $0.5\;{\mu}m$ BiCMOS(Bipolar-CMOS) 공정 파라미터를 사용하여 설계되었으며, 시뮬레이션은 Cadence사의 Spectre를 이용하였다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.923-926
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• 2003

This paper presents a novel low voltage reference circuit under the MOS threshold voltage(V$_{th}$) in standard CMOS process. It is based on the weighted difference of the gate-source voltages of an NMOS and a PMOS operating in saturation region. The voltage reference is designed for low power OLED driver ICs. The proposed circuit is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The minimum supply voltage is 2V, and the typical temperature coefficient is 99.6ppm/ C.C.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.98-106
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• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.728-735
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• 2016

A 70 MHz temperature-compensated on-chip CMOS relaxation oscillator for mobile display driver ICs is proposed to reduce frequency variations. The proposed oscillator compensates for frequency variation with respect to temperature by adjusting the bias currents to control the change in delay of comparators with temperature. A bandgap reference (BGR) is used to stabilize the bias currents with respect to temperature and supply voltages. Additional temperature compensation for the generated frequency is achieved by optimizing the resistance in the BGR after measuring the output frequency. In addition, a trimming circuit is implemented to reduce frequency variation with respect to process. The proposed relaxation oscillator is fabricated using 45 nm CMOS technology and occupies an active area of $0.15mm^2$. The measured frequency variations with respect to temperature and supply voltages are as follows: (i) ${\pm}0.23%$ for changes in temperature from -30 to $75^{\circ}C$, (ii) ${\pm}0.14%$ for changes in $V_{DD1}$ from 2.2 to 2.8 V, and (iii) ${\pm}1.88%$ for changes in $V_{DD2}$ from 1.05 to 1.15 V.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.62-68
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• 1989

In this paper, Analog/Digital BCDMOS technology that the bipolar devices for driver applications CMOS devices for logic applications, and DMOS devices for high voltage applications is pressented. An optimized poly-gate p-well CMOS process is chosen to fabricate the BCDMOS, and the basic concepts to desigh these devices are to improve the characteristics of bipolar, CMOS & DMOS with simple process technology. As the results, $h_{FE}$ value is 320 (Ib-$10{\mu}A$ for bipolar npn transistor, and there is no short channel effects for CMOS devices which have Leff to $1.25{\mu}m$ and $1.35{\mu}m$ for n-channel and p-channel, respectively. Finally, breakdown voltage is obtained higher than 115V for DMOS device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.189-196
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• 1989

In this paper, BICMOS gate array technology that has CMOS devices for logic applications and bipolar devices for driver applications is presented. An optimized poly gate p-well CMOS process is chosen to fabricate the BICMOS gate array system and the basic concepts to design these devices are to improve the characteristics of bipolar & CMOS device with simple process technology. As the results hFE value is 120(Ic=1mA) for transistor, and there is no short channel effects for CMOS devices which have Leff to 1.25um and 1.35um for n-channel, respectively, 0.8nx gate delay time of 41 stage ring oscillators is obtained.