• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.125-129
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• 2008

A low-voltage active CMOS inductor approach, which can improve the quality-factor(Q), is proposed in this paper. A low-voltage active inductor circuit topology with a feedback resistance is proposed, which can substantially improve its equivalent inductance and quality-factor(Q). This proposed low-voltage active inductor with a feedback resistance was simulated by ADS(Agilent) using 0.18um standard CMOS technology. Simulation showed that the designed active inductor had a maximum quality-factor(Q) of 3000 with a 1.5nH inductance at 4GHz

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.345-348
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• 2002

A complementary VHF CMOS active inductor is described. The proposed circuit employs 'p-type' and 'n-type' active inductor to obtain enlarged signal handling ability. Under the same inductance, Q value, and power consumption, the proposed circuit shows more than 12-㏈ improvement in dynamic range while maintaining high-frequency operation. Further enhancement is obtained by using a fully differential floating inductor structure. A 1-㎓ 4$\^$th/-order coupled-resonator filter is designed to demonstrate the potential of the proposed active inductor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.897-904
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• 2011

In this paper, a novel circuit topology of a low-noise amplifier tunable at 1.8GHz band for PCS and 2.4GHz band for WLAN using a CMOS active inductor is proposed. This circuit topology to reduce higher noise figure of the low noise amplifier with the CMOS active load is analyzed. Furthermore, the noise canceling technique is adopted to reduce more the noise figure. The noise figure of the proposed circuit topology is analyzed and simulated in $0.18{\mu}m$ CMOS process technology. Thus, the simulation results exhibit that the noise performance enhancement of the tunable low noise amplifier is about 3.4dB, which is mainly due to the proposed new circuit topology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.877-882
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• 2016

In this paper, a novel CMOS high Q factor 2-port active inductor has been proposed. The proposed circuit is designed by cascading basic gyrator-C structural active inductors and attaching the feedback LC resonance circuit. This LC resonator can compensate parasitic capacitance of transistor and can improve Q factor over wide frequency range. The proposed circuit was fabricated and simulated using 65 nm Samsung RF CMOS process. The fabricated circuit shows inductance of above 2 nH and Q factor higher than 40 in the frequency range of 1~6 GHz.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.89-92
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• 2008

CMOS 기반의 고주파 집적회로에서는 높은 이득과 출력을 얻기 위하여 인덕터와 같은 수동소자를 사용한다. 그러나 수동소자를 사용하게 되면 넓은 면적을 차지하기 때문에 회로의 크기를 증가시키는 단점을 갖는다. 본 논문에서는 PMOS 를 기반으로 구현한 active inductor 를 적용하여 회로의 면적을 줄일 수 있으며, 기존의 주파수 변환기와 동등한 선형 특성을 갖는 상향 주파수 변환기를 설계하였다. 인덕터를 적용한 상향 주파수 변환기의 OIP3 ($3^{rd}$ Output Intercept Point)는 1.3 dBm 을 가지며, 제안한 상향 주파수 변환기의 OIP3 는 0.8 dBm 으로 동등한 선형 특성을 보이며, layout 상에서 회로의 면적을 40 % 이상 감소하는 특성의 선형 송신기용 주파수 변환기를 설계 분석하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.9 s.100
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• pp.957-963
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• 2005

This paper presents technique of wideband TIA for optical communication systems using TSMC 0.25 ${\mu}m$ CMOS RF-Mixed mode. In order to improve bandwidth characteristics of an TIA, we use active inductor shunt peaking to cascode and common-source configuration. The result shows the 37 mW and 45 mW power dissipation with 2.5 V bias and 61 dB$\Omega$ and 61.4 dB$\Omega$ transimpedance gain. And the -3 dB bandwidth of the TIA is enhanced from 0.8 GHz to 1.45 GHz in cascode and 0.61 GHz to 0.9 GHz in common-source. And the input noise current density is $5 pA/\sqrt{Hz}$ and $4.5 pA/\sqrt{Hz}$, and -10 dB out put return loss is obtained in 1.45 GHz. The total size of the chip is $1150{\times}940{\mu}m^2$.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.283-286
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• 1999

A 2㎓, low noise, low power CMOS voltage-controlled oscillator (VCO) with an integrated LC resonator is presented. The design of VCO relies heavily on the on-chip spiral inductor. An optimized spiral inductor with Q-factor of nearly 8 is achieved and used for the VCO. The simulated result of phase noise is as low as -l14 ㏈c/Hz at an offset frequency of a 600KHz from a 2㎓ carrier frequency. The VCO is tuned with standard available junction capacitors, resulting in an about 400MHz tuning range (20%). Implemented in a five-metal 0.25${\mu}{\textrm}{m}$ standard CMOS process, the VCO consumes only 2㎽ from a single 2.5V supply. It occupies an active area of 620${\mu}{\textrm}{m}$$\times$720${\mu}{\textrm}{m}$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.143-148
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• 2015

In this paper a new method is proposed for realizing active floating inductors from voltage differencing transconductance amplifier(VDTA) which is being studied nowadays. This proposed method employs only one VDTA and one transconductance for designing an active inductor from a passive floating inductor and implementing it to integrated circuits. The number of CMOS transistors can be considerably reduced from 6~18 as 1~3 gm circuits can be eliminated and even without R the design can be made, which can help in reducing the size of the circuit and power consumption. The proposed VDTA floating inductor was successfully used in constructing 1 MHz second order biquad active bandpass filter and bandwidth could be adjusted from 77kHz~1.59MHz by the changes made in gm from 6uS~20uS.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.198-206
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• 2013

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ${\mu}m$ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ${\mu}m$ process and the die area of the solenoid inductor is 0.013 $mm^2$. The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.311-320
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• 2008

In this paper, a new variable active inductor using a conventional grounded active inductor with feedback variable LC-resonator is proposed. The grounded active inductor is realized by the gyrator-C topology and the variable LC-resonator is realized by the low-Q spiral inductor and varactor. This variable LC-resonator can compensate the degradation of Q-factor due to parasitic capacitance of a transistor, and the frequency range with high Q-factor is adjustable by resonance frequency adjustment of LC-resonator. The fabricated variable active inductor with Magnachip $0.18{\mu}m$ CMOS process shows that high-Q frequency range can be adjusted according to varactor control voltage from 4.66 GHz to 5.45 GHz and Q-factor is higher than 50 in the operating frequency ranges. The measured inductance at 4.9GHz can be controlled from 4.12 nH to 5.97 nH by control voltage.