• Journal of IKEEE
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• v.20 no.4
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• pp.428-431
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• 2016

Power semiconductor devices had been producted with bipolar only processes, but Bipolar-CMOS-DMOS(BCD) processes have been adapted recently to fabricate these devices since most foundry companies have provided BCD processes instead of Bipolar only processes. In this study, Regulator and OP Amp are used as most popular design IPs and BCD processes for the designing are converted from bipolar only processes. Power Switching Sensor(PSS) ICs are designed specifically and fabricated on a silicon chip. The operation results of the packaged chip show the good matching with test results of the simulation.

• ETRI Journal
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• v.31 no.6
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• pp.717-724
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• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.443-446
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• 2004

Short channel IC circuits become increasingly important in modern high performance electronic systems. In this paper, parts of an analog hearing aid, an amplifier and a regulator, which are implemented with short channel CMOS devices, are designed and optimized in its performance.

• Journal of electromagnetic engineering and science
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• v.14 no.2
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• pp.61-67
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• 2014

This paper presents a zero-IF CMOS RF receiver, which supports three channel bandwidths of 5/10/40MHz for LTE-Advanced systems. The receiver operates at IMT-band of 2,500 to 2,690MHz. The simulated noise figure of the overall receiver is 1.6 dB at 7MHz (7.5 dB at 7.5 kHz). The receiver is composed of two parts: an RF front-end and a baseband circuit. In the RF front-end, a RF input signal is amplified by a low noise amplifier and $G_m$ with configurable gain steps (41/35/29/23 dB) with optimized noise and linearity performances for a wide dynamic range. The proposed baseband circuit provides a -1 dB cutoff frequency of up to 40MHz using a proposed wideband OP-amp, which has a phase margin of $77^{\circ}$ and an unit-gain bandwidth of 2.04 GHz. The proposed zero-IF CMOS RF receiver has been implemented in $0.13-{\mu}m$ CMOS technology and consumes 116 (for high gain mode)/106 (for low gain mode) mA from a 1.2 V supply voltage. The measurement of a fabricated chip for a 10-MHz 3G LTE input signal with 16-QAM shows more than 8.3 dB of minimum signal-to-noise ratio, while receiving the input channel power from -88 to -12 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.44-54
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• 2001

In this paper, a novel test method is proposed to detect the hard and soft fault in analog circuits. The proposed test method makes use of the offset voltage, which is one of the op-amps characteristics. During the test mode, CUT is modified to unit gain op-amps with feedback loop. When the input of the op-amp is grounded, a good circuit has a small offset voltage, but a faulty circuit has a large offset voltage. Faults in the op-amp which cause the offset voltage exceeding predefined range of tolerance can be detected. In the proposed method, no test vector is required to be applied. Therefore the test vector generation problem is eliminated and the test time and cost is reduced. In this note, the validity of the proposed test method has been verified through the example of the dual slope A/D converter. The HSPICE simulations results affirm that the presented method assures a high fault coverage.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.137-144
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• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.403-406
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• 1987

CMOS operational amplifier is most useful building bloch in analog circuit. This paper represents the analysis and design method of CMOS OP AMP to use general purpose such as the A/D and D/A converter, PCM encoder and decoder etc. The required specifications is obtained by changing W/L ration of CMOS devices. The design procedure must be iterative in as much as it is almost impossible to relate all specifications simultaneously. This is performanced with IBM-PC XT by using SPICE(SIMULATION PROGRAM WITH INTEGRATED CIRCUIT EMPHASIS)program.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.678-684
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• 2013

This paper describes a low-power baseband circuit for SAW-less LTE-Advanced transmitters. The proposed transmitter baseband circuit consists of a 2nd-order Tow-Thomas type active RC-LPF and a 1st-order passive RC LPF. It can provide a 7 multi-channel cut-off frequencies and wide gain control range of -41 dB ~ 0 dB with a 1-dB step. The proposed 2nd-order active RC-LPF adopts an op-amp in which three other sub-op amps are in parallel connected to reduce DC current for different cutoff frequency. In addition, each sub-op amp adopts both Miller and feed-forward phase compensation method to achieve an UGBW of more than 1-GHz with a small DC power consumption. The proposed baseband circuit is implemented in 65-nm CMOS technology, consuming DC power from 6.3 mW to 24.1 mW from a 1.2V supply voltage for each different cut-off frequency.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1120-1122
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• 1995

This paper presents a 2-stage, simple, power-efficient 3V CMOS operational amplifier and its equation based design optimization. Because of its simple structure, it is very suitable as a VLSI library cell in analog/digital mixed-mode systems. The op-amp, which contains a constant-$g_m$ rail-to-rail input stage and a simple feedforward class-AB rail-to-rail output stage, is analyzed and the results are presented in the form of design equations and procedures, which provide an insight into the trade-offs among performance requirements. The results of SPICE simulations are shown to agree very welt with the use of design equations.

• ETRI Journal
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• v.29 no.2
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• pp.212-218
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• 2007

A novel low-voltage CMOS current feedback operational amplifier (CFOA) is presented. This realization nearly allows rail-to-rail input/output operations. Also, it provides high driving current capabilities. The CFOA operates at supply voltages of ${\pm}0.75V$ with a total standby current of 304 ${\mu}A$. The circuit exhibits a bandwidth better than 120 MHz and a current drive capability of ${\pm}1$ mA. An application of the CFOA to realize a new all-pass filter is given. PSpice simulation results using 0.25 ${\mu}m$ CMOS technology parameters for the proposed CFOA and its application are given.