• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.224-227
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• 1999

This paper presents a design of the real-time preprocessor for CMOS image sensor suitable to the digital camera applications. CMOS image sensor offers some advantages in on-chip integration, system power reduction, and low cost. However, it has a lower-quality image than CCDs. We describe an image enhancement algorithm, which includes color interpolation, color correction, gamma correction, sharpening, and automatic exposure control, to compensate for this disadvantage, and present its efficient hardware architecture to implement on the real-time processor. The presented real-time preprocessor was designed using VHDL, and it contains about 19.2K logic gates. We also implement our system on FPGA chips in order to provide the real-time adjustment and it was successfully tested.

• Journal of the Optical Society of Korea
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• 제19권6호
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• pp.658-664
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• 2015

Lens designers generally refer to flat image fields and attempt to minimize the field curvature. Present-day CMOS image sensors for mobile phone cameras, however, are not flat, but curved. Sometimes it is necessary to generate an intentional field curvature according to the degree and direction of the CMOS image-sensor’s curvature. This paper presents the degree of curvature of a CMOS image sensor measured using an interferometer, and proposes an effective compensation method that minimizes the net field curvature through optimizing the air gap between lens elements, which is demonstrated using simulations and experiments.

• 한국항공우주학회지
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• 제33권10호
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• pp.93-97
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• 2005

본 논문은 과학기술위성2호 핵심우주기술시험용 탑재체인 고 정밀 디지털 태양센서의 개발에 관한 것이다. 고 정밀 디지털 태양센서는 국내 최초의 디지털 태양센서로서 CMOS image sensor를 이용한다. FDSS는 광학부, FPGA(Field Programable Gate Array)부 및 MCU(Micro controller unit)부로 구성되어있다. 본 논문에서는 구경(Aperture)의 설계와 관련된 광학부의 광학특성 분석에 중점을 두어 기술하고자 한다. 또한 CMOS image sensor(CIS) 화소 면에 투사되는 태양광의 광학적 특성도 분석한다.

• 센서학회지
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• 제14권6호
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• pp.387-394
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• 2005

In order to design SOI CMOS image sensors, SOI MOSFET model parameters were extracted using the equation of bulk MOSFET model parameters and were optimized using SPICE level 2. Simulated I-V characteristics of the SOI NMOSFET using the extracted model parameters were compared to the experimental I-V characteristics of the fabricated SOI NMOSFET. The simulation results agreed well with experimental results. A unit pixel for SOI CMOS image sensors was designed and was simulated for the PPS, APS, and logarithmic circuit using the extracted model parameters. In these CMOS image sensors, a nano-wire MOSFET photodetector was used. The output voltage levels of the PPS and APS are well-defined as the photocurrent varied. It is confirmed that SOI CMOS image sensors are faster than bulk CMOS image sensors.

• Journal of Astronomy and Space Sciences
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• 제18권3호
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• pp.231-238
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• 2001

CMOS (complementary metal oxide semiconductor) 영상센서를 이용한 영상관측 시스템 을 제작하여 천문관측 활용 가능성에 대한 조사를 수행하였다. CCD(charge coupled device) 영상센서는 지난 30여년간 개발을 거듭해온 결과, 대부분의 영상획득장비나 천문관측용으로 사용되는 극미광 영상장비로 사용되왔다. 그러나 CMOS영상센서 가 실용화되면서 CCD를 이용한 극미광 영상관측 시스템과 일반 상용 영상시스템은 CMOS 영상센서로 교체되고 있다. CMOS 영상센서의 경우 CCD에 비해 시스템 잡음과 측광 성능은 뒤지지만, 태양과 별의 영상을 얻어본 결과 일반적인 영상관측장비로서는 사용이 가능하다.

• 전기전자학회논문지
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• 제24권4호
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• pp.942-949
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• 2020

본 논문에서는 column-parallel readout 회로에 적합하도록 개선된 CMOS 이미지 센서용 algorithmic ADC를 제안한다. 커패시터의 비율과 무관하고 연산 증폭기의 이득에 둔감하면서 증폭기 하나로 동작 할 수 있도록 기존 algorithmic ADC를 수정하고 적응형 바이어싱을 적용한 증폭기를 사용하여 높은 변환효율을 갖도록 하였다. 제안하는 ADC는 0.18-㎛ 매그나칩 CMOS 공정으로 설계되었으며, Spectre 시뮬레이션을 통해 기존 algorithmic ADC에 비해 변환속도당 전력소모가 37% 줄어 들었음을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• 전기전자학회논문지
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• 제11권1호통권20호
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• Current Optics and Photonics
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• 제7권2호
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• pp.200-206
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• 2023

Near-infrared (NIR) sensing technology using CMOS image sensors is used in many applications, including automobiles, biological inspection, surveillance, and mobile devices. An intuitive way to improve NIR sensitivity is to thicken the light absorption layer (silicon). However, thickened silicon lacks NIR sensitivity and has other disadvantages, such as diminished optical performance (e.g. crosstalk) and difficulty in processing. In this paper, a pixel structure for NIR sensing using a stacked CMOS image sensor is introduced. There are two photodetection layers, a conventional layer and a bottom photodiode, in the stacked CMOS image sensor. The bottom photodiode is used as the NIR absorption layer. Therefore, the suggested pixel structure does not change the thickness of the conventional photodiode. To verify the suggested pixel structure, sensitivity was simulated using an optical simulator. As a result, the sensitivity was improved by a maximum of 130% and 160% at wavelengths of 850 nm and 940 nm, respectively, with a pixel size of 1.2 ㎛. Therefore, the proposed pixel structure is useful for NIR sensing without thickening the silicon.

• International Journal of Aeronautical and Space Sciences
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• 제13권2호
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• pp.260-265
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• 2012

Satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2). Based on the mission requirements of STSAT-2, the conventional analog-type sun sensors were found to be inadequate, motivating the development of a compact, fast and fine digital sun sensor (FDSS). The FDSS uses a CMOS image sensor and has an accuracy of less than 0.03degrees, an update rate of 5Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize its weight. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA), which acquires images from the CMOS sensor, and stores and processes the image data. The sensor accuracy is maintained by a rigorous centroid algorithm. This paper describes the FDSS designs, realizations, tests and calibration results.