• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.32-37
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• 2007

A DMB CMOS power amplifier (PA) with high efficiency and linearity is present. For this work, a 0.13-um standard CMOS process is employed and all components of the proposed PA are fully integrated into one chop including output matching network and adaptive bias control circuit. To improve the efficiency and linearity simultaneously, an adaptive bias control circuit is adopted along with second harmonic termination circuit at the drain node. The PA is shown a $P_{1dB}$ of 16.64 dBm, power added efficiency (PAE) of 38.31 %, and power gain of 24.64 dB, respectively. The third-order intermodulation (IMD3) and the fifth-order intermodulation (IMD5) have been -24.122 dBc and -37.156 dBc, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.48-55
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• 1999

This paper describes automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems. The required gain of the AGC in the proposed system is controlled directly by digital bits without conventional extra D/A converters and the signal settling behavior is almost independent of AGC gain variation at video speeds. A capacitor-segment combination technique to obtain large capacitance values considerably improves the effective bandwidth of the AGC based on switched-capacitor techniques. A proposed layout scheme for capacitor implementation shows AGC matching accuracy better than 0.1 %. The outputs from the AGC are transferred to a 10b A/D converter integrated on the same chip. The proposed AGC is implemented as a sub-block of a CCD camera interface system using a 0.5 um n-well CMOS process. The prototype shows the 32-dB AGC dynamic range in 1/8-dB steps with 173 mW at 3 V and 25 MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.59-65
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• 1998

In this paper, a novel rail-to-rail input stage circuit with improved transconductance Is designed. Its excellent performances over whole common-mode input voltage Vcm range is demonstrated by circuit simulator HSPICE. The novel input stage circuit comprises additional 4 input transistors and 4 current sources/sinks. It maintains DC currents of signal amplifying transistors when one of the differential input stage circuits operates, but it reduces these currents to 1/4 when both differential input stage circuits operates, As a result, a operational amplifier with the novel circuit maintains nearly constant transconductance performance and unity-gain frequency in strong inversion region. The novel circuit allows an optimal frequency compensation and uniform operational amplifier performance over whole Vcm range.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.76-82
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• 2002

This paper presents a quaternary-binary decoder, a quaternary logic current buffer, and a quaternary logic full-adder using current-mode multiple-valued logic CMOS circuits. Proposed full-adder requires only 15 MOSFET, 60.5% and 48.3% decrease of devices are achieved compared with conventional binary CMOS full-adder and Current's full-adder. Therefore, decrease of area and internal nods are achieved. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 1.5 ns of propagation delay and 0.42㎽ of power consumption. Also, proposed full-adder can easily adapted to binary system by use of encoder, designed decoder and designed current buffer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.42-48
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• 1990

In this paper robust test generation for stuck-open faults in CMOS circuits is proposed. By obtaining initialization patterns and test patterns using the relationship of bit position and Hamming weight among input vectors for CMOS circuit test generation time for stuck-open faults can be reduced, and the problem of input transition skew which make fault detection difficult is solved, and the number of test sequences are minimized. Also the number of test sequences is reduced by arranging test sequences using Hamming distance between initialization patterns and test patterns for circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.57-57
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• 2001

본 논문에서는 RFID를 위한 읽기 전용 CMOS 트랜스폰더를 one-chip으로 설계하였다. 리더에서 공급되는 자기장으로부터 트랜스폰더 칩의 전원을 공급하기 위한 전파정류기를 NMOS 트랜지스터를 사용하여 설계하였으며, 데이터 저장 소자로는 64비트의 ROM을 사용하였다. 메모리에 저장되어 있는 ID 코드는 Manchester 코딩되어 front-end 임피던스 변조 방식으로 리더에 전송된다. 임피던스 변조를 위한 감폭회로로는 리더와 트랜스폰더 사이의 거리가 변해도 일정한 감폭율을 갖는 새로운 감폭회로를 사용하였다. 설계된 회로는 0.65㎛ 2-poly, 2-metal CMOS 공정을 사용하여 IC로 제작되었다. 칩 면적은 0.9㎜×0.4㎜이다. 측정 결과 설계된 트랜스폰더 IC는 인식거리 내에서 약 20∼25%의 일정한 감폭율을 보이며, 125㎑의 RF에 대해 3.9kbps의 데이터 전송속도를 보인다. 트랜스폰더 칩의 전력소모는 읽기 모드시 약 100㎼이다. 인식거리는 약 7㎝이다.

• Electronics and Telecommunications Trends
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• v.23 no.6
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• pp.81-91
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• 2008

CMOS 공정의 가속적인 스케일링에 의해 CMOS 기술은 종래의 마이크론기술에서 나노기술로 변해가고 있다. 이러한 반도체 소자 및 제작기술에 따른 온도와 공정의 변화에 매우 민감한 부분인 아날로그 회로는 설계 초기단계에서 중요한 요소들(이득, 누설 전류, 잡음 및 부정합 등)을 재검토할 필요가 있다. 또한, 나노 CMOS 공정을 사용한 1.0 V 이하의 저전압 동작에서는 아날로그 신호의 동적영역 확보가 어렵고 잡음이 증가하므로 새로운 패러다임을 적용한 혁신적인 아날로그 회로기술 개발이 필요한 실정이다. 이에 따라, 본 고에서는 그린기술(green technology)의 한 요소로서, 나노 CMOS 공정기술을 이용한 1.0 V 이하 전원전압의 저전력 아날로그 회로기술 동향과 관련 특허동향에 대해서 살펴보고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.949-954
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• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.55-63
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• 1999

A new CMOS If Package design methodology is presented, analyzing the electrical characteristics of a package and its effects on the CMOS digital circuits. An analytical investigation of the package noise effects due to the simultaneous switching of the gates within a chip, i.e., simultaneous switching noise (SSN) is performed. Then not only are novel design formula to meet electrical constraints of the Package derived, but also package design methodology based on the formula is proposed. Further, in order to demonstrate the Proposed design methodology, the design results are compared with HSPICE (a general purpose circuit simulator) simulation for $0.3\mu\textrm{m}$-based CMOS circuits. According to the proposed design procedures, it is shown that the results have excellent agreements with those of HSPICE simulation.