• The Journal of the Korea Contents Association
• /
• v.6 no.9
• /
• pp.98-107
• /
• 2006

By improving performance of mobile machine(3D engine, 3D accelerator chip set, etc) and developing wireless network technology, a demand for actual contents of users is being increased rapidly. But, there are some difficulties yet for the speedy development of actual contents because of the limitation of development resources that is dependent on each mobile device's different performance. In general, much of the animated character-creation work for mobile environment is still done manually by experienced animator with the method of key frame processing. However, it needs a lot of time and more costs for creating motion. Additionally, it is possible to cause a distortion of motion. In this paper, I solved the difficulties by using a optical motion capture system, it was able to acquire accurate motion data more easily and quickly, and then it was possible to make 3D dance contents efficiently. Also, I showed techniques of key reduction and controlling frame number for using huge amounts of motion capture data in mobile environment which requires less resources. In making 3D dance contents, using an optical motion capture system was verified that it was more efficient to make and use actual-reality contents by creating actual character motion and by decreasing processing time than existing method.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.1
• /
• pp.62-74
• /
• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• Proceedings of the Korean Society for Bioinformatics Conference
• /
• 2006.02a
• /
• pp.109-114
• /
• 2006

최근 Human 지놈 프로젝트를 포함한 다양한 종의 지놈 프로젝트가 수행되고 수많은 지놈정보가 생산되고 있으며 이를 해석하고 서로 연관성를 찾기 위한 다양한 연구가 진행되고 있다. 즉 최신 생명공학과 관련된 연구방향이 DNA의 구조적 해석에서 기능 해석과 유전자들의 상호연관성을 규명하는 방향으로 변화하고 있으며 이를 위한 강력한 도구로서 DNA microarray (DNA chip)는 방대한 양의 지놈 정보를 이용하여 단시간에 대량으로 고속처리하여 효율적으로 유전자 기능을 분석할 수 있는 주목받고 있는 방법이다. DNA microarray 실험과 분석에 있어 데이터분석, 재현성, 종간의 비교, 확인실험 및 비용 등의 문제가 있지만 유전자발현양상 데이터로부터 정확한 환자의 예후를 예측할 수 있는 비교적 적은 유전자 그룹의 진단마커를 찾거나, 하나의 유전자가 아니라 mouse 전체 지놈의 유전자발현 패턴을 인간의 암을 위시한 각종 질병 연구를 위한 발현 신호나 변화 등을 발견하여 신약개발 등에 활용하고자 하는 시도가 활발히 진행되고 있다. 서로 다른 종간에 비슷한 phenotype의 유전자발현도 진화적으로 보존되었다는 전제 하에서 지놈 sequence의 비교연구가 가능하고 DNA microarray 발현 데이터에 근거하여 독립적으로 각 종간의 유전자발현패턴을 비교함으로써 난치병 등을 새롭게 분류할 수 있다. 즉, 암세포 등에서 유전자발현 양상은 유전학적, 환경적 alteration들이 잘 반영되어 있다고 간주하고, 이러한 양상을 바탕으로 인간의 암을 위시한 다양한 질병 연구를 위한 최적의 mouse 모델을 찾을 수 있고, 이는 결국 새로운 치료 방법 개발이나 맞춤의학 실현에 중요한 역할을 할 것으로 기대된다. 특히 pathway 타겟으로 하는 치료를 위해서는 Human-mouse 비교를 통한 발현 신호를 찾는 것이 진단에서는 매우 유용한 방법이다. 이를 위한 고성능의 분석방법이나 시스템의 개발이 중요하게 된다.. 관류의 정도와 조영증강정도를 중심으로 관류 MR 영상소견과 조직학적 소견을 관련지어 분석하였다. 결과: 조영증강 T1강조MR영상에서 환상조영증강을 보이는 다형성 교보세포종 2예에서는 변연부 외륜이 고관류를, 중심부의 괴사부위는 저관류로 나타났다. 저등급 교종은 경계가 불분명한 저관류부위로 보였다. 뇌농양 2예는 변연부 외륜이 경도의 고관류를, 중심부는 저관류로 나타났다. 뇌수막종은 미만성의 균일한 중등도 혹은 고도의 고관류로 보였으며, 임파종과 배아종은 경계가 명확한 저관류부위로 나타났다. 신경세포종은 종괴\ulcorner 일부에 중등도 혹은 고도의 고관류부위가 관찰되었고, 전이암은 다수병변중 일부에서 중등도의 고관류를 보였다. 방사선괴사는 저관류부위내에 국소적 고관류부위를 보였다. 결론: 관류 MR영상은 뇌종양의 관류상태를 비교적 잘 반영하며, 조직학적 특성을 예측하는데에 도움을 주 수 있을 것으로 기대된다. 뇌종야에서의 관류MR영상의 분명한 역할을 규명하기 위해서는 앞으로 더 많은 임상적 연구가 필요할 것으로 생각된다.조증 환자의 자극성 전타액내 lactobacilli양은 peroxidase system을 함유한 세치제를 사용한 군에서 대조군에 비해 상대적으로 낮게 나타났으나(p = 0.067) 통계학적 유의성은 없었다.같은 예에서 찾아 볼 수 있다. 첫째, 발음상으로 동사의 변화형에서 "porte[$p{\jmath}rte$](들다: 현재형), porte[$p{\jmath}rte$](과거분사형), porta[$p{\jmath}rte$](단순과거형)"등이 대립되며, 이휘 "Porto[$p{\jmath}rte$](포르토)"와도 대립된다. 둘째, 어휘적 대립 "le haut[$l{\partial}o$](위)/l'eau[lo](물)"와 형태론적 대립 "le[$l{\partial}$](정관사, 남성단수)/l

• Journal of the Microelectronics and Packaging Society
• /
• v.9 no.3
• /
• pp.19-23
• /
• 2002

This paper presents a micro fluxgate magnetic sensor in printed circuit board (PCB). In order to observe the effect of the closed magnetic path, the magnetic cores of rectangular-ring and two bars were each fabricated. Each fluxgate sensor consists of five PCB stack layers including one layer magnetic core and four layers of excitation and pick-up coils. The center layer as a magnetic core is made of a Co-based amorphous magnetic ribbon with extremely high DC permeability of ~100,000. Four outer layers as an excitation and pick-up coils have a planar solenoid and are made of copper foil. In case of the fluxgate sensor having the rectangular-ring shaped core, excellent linear response over the range of -100 $\mu$T to ＋ 100 $\mu$T is obtained with 540 V/Tsensitivity at excitation square wave of 3 $V_{p-p}$ and 360 KHz. The chip size of the fabricated sensing element is $7.3 \times 5.7\textrm{mm}^2$. The very low power consumption of ~8 mW was measured. This magnetic sensor is very useful for various applications such as: portable navigation systems, telematics, VR game and so on.n.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.1
• /
• pp.47-53
• /
• 2012

Bonding strength of Sn-3.0Ag-0.5Cu solder joint due to degradation characteristic of OSP surface finish was investigated, compared with SnPb finish. The thickness variation and degradation mechanism of organic solderability preservative(OSP) coating were also analyzed with the number of reflow process. To analyze the degradation degree of solder joint strength, FR-4 PCB coated with OSP and SnPb were experienced preheat treatment as a function of reflow number from 1st to 6th pass, respectively. After 2012 chip resistors were soldered with Sn-3.0Ag-0.5Cu on the pre-heated PCB, the shear strength of solder joints was measured. The thickness of OSP increased with increase of the number of reflow pass by thermal degradation during the reflow process. It was also observed that the preservation effect of OSP decreased due to OSP degradation which led Cu pad oxidation. The mean shear strength of solder joints formed on the Cu pads finished with OSP and SnPb were 58.1 N and 62.2 N, respectively, through the pre-heating of 6 times. Although OSP was degraded with reflow process, the feasibility of its application was proven.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.10
• /
• pp.95-104
• /
• 2004

This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.5 s.347
• /
• pp.54-63
• /
• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.6 s.348
• /
• pp.47-52
• /
• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.6 s.348
• /
• pp.53-61
• /
• 2006

In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.10
• /
• pp.36-42
• /
• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.