• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.927-934
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• 2019

Recently, mobile devices have evolved into small computers with various functions according to user requirements. Careful attention must be paid to the design of the power supply network for the stable operation of the application processor (AP), the wireless communication modem, the high performance camera, and the various interfaces of the mobile device to implement various functions of the mobile device. In this paper, we analyzed and verified the method of optimizing the design parameters such as the position, capacity, and number of decoupling capacitors to meet the target impedance required by the driver IC chip to ensure the stability of the power supply network of mobile devices that should be designed as wiring type due to mounting density limitation. The proposed wired power supply network design method can be applied to various applications including high-speed signal transmission line in addition to mobile applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.397-400
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• 2009

This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.

• Smart Structures and Systems
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• v.6 no.5_6
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• pp.579-593
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• 2010

Low-power radio frequency (RF) chip transceiver technology and the associated structural health monitoring platforms have matured recently to enable high-rate, lossless transmission of measurement data across large-scale sensor networks. The intrinsic value of these advanced capabilities is the allowance for high-quality, rapid operational modal analysis of in-service structures using distributed accelerometers to experimentally characterize the dynamic response. From the analysis afforded through these dynamic data sets, structural identification techniques can then be utilized to develop a well calibrated finite element (FE) model of the structure for baseline development, extended analytical structural evaluation, and load response assessment. This paper presents a case study in which operational modal analysis is performed on a three-span prestressed reinforced concrete bridge using a wireless sensor network. The low-power wireless platform deployed supported a high-rate, lossless transmission protocol enabling real-time remote acquisition of the vibration response as recorded by twenty-nine accelerometers at a 256 Sps sampling rate. Several instrumentation layouts were utilized to assess the global multi-span response using a stationary sensor array as well as the spatially refined response of a single span using roving sensors and reference-based techniques. Subsequent structural identification using FE modeling and iterative updating through comparison with the experimental analysis is then documented to demonstrate the inherent value in dynamic response measurement across structural systems using high-rate wireless sensor networks.

• Journal of the Korean Solar Energy Society
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• v.38 no.3
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• pp.21-28
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• 2018

The objects of PV (Photovoltaic) monitoring system is to reduce the loss of system and operation and maintenance costs. In case of PV plants with configured of centralized inverter type, only 1 PV module might be caused a large loss in the PV plant. For this reason, the monitoring technology of PV module-level that find out the location of the fault module and reduce the system losses is interested. In this paper, a fault diagnosis algorithm are proposed using thermal and electrical characteristics of PV modules under failure. In addition, the monitoring system applied with proposed algorithm was constructed. The wireless sensor using LoRa chip was designed to be able to connect with IoT device in the future. The characteristics of PV module by shading is not failure but it is treated as a temporary failure. In the monitoring system, it is possible to diagnose whether or not failure of bypass diode inside the junction box. The fault diagnosis algorithm are developed on considering a situation such as communication error of wireless sensor and empirical performance evaluation are currently conducting.

• KSCI Review
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• v.14 no.1
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• pp.265-271
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• 2006

In this paper, we propose a new automatic fingerprint identification system that identifies individuals in large databases. The algorithm consists of three steps: preprocessing, classification, and matching, in the classification, we present a new classification technique based on the statistical approach for directional image distribution. In matching, we also describe improved minutiae candidate pair extraction algorithm that is faster and more accurate than existing algorithm. In matching stage, we extract fingerprint minutiaes from its thinned image for accuracy, and introduce matching process using minutiae linking information. Introduction of linking information into the minutiae matching process is a simple but accurate way, which solves the problem of reference minutiae pair selection in comparison stage of two fingerprints quickly. This algorithm is invariant to translation and rotation of fingerprint. The proposed system was tested on 1000 fingerprint images from the semiconductor chip style scanner. Experimental results reveal false acceptance rate is decreased and genuine acceptance rate is increased than existing method.

• Journal of the Korea Society of Computer and Information
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• v.25 no.4
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• pp.1-9
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• 2020

In this paper, we propose Dynamic Rank Subsetting (DRAS) technique that enhances the energy-efficiency and the performance of memory system through the data compression. The goal of this technique is to enable a partial chip access by storing data in a compressed format within a subset of DRAM chips. To this end, a memory rank is dynamically configured to two independent sub-ranks. When writing a data block, it is compressed with a data compression algorithm and stored in one of the two sub-ranks. To service a memory request for the compressed data, only a sub-rank is accessed, whereas, for a memory request for the uncompressed data, two sub-ranks are accessed as done in the conventional memory systems. Since DRAS technique requires minimal hardware modification, it can be used in the conventional memory systems with low hardware overheads. Through experimental evaluation with a memory simulator, we show that the proposed technique improves the performance of the memory system by 12% on average and reduces the power consumption of memory system by 24% on average.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.251-262
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• 2019

In this paper, we propose a simulator that provides various algorithms of RBF networks on neuromorphic chips. To develop algorithms based on neuromorphic chips, the disadvantages of using simulators are that it is difficult to test various types of algorithms, although time is fast. This proposed simulator can simulate four times more types of network architecture than existing simulators, and it provides an additional a two-layer structure algorithm in particular, unlike RBF networks provided by existing simulators. This two-layer architecture algorithm is configured to be utilized for multiple input data and compared to the existing RBF for performance analysis and validation of utilization. The analysis showed that the two-layer structure algorithm was more accurate than the existing RBF networks.

• Journal of Convergence for Information Technology
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• v.11 no.9
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• pp.124-129
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• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

• Journal of Korean Society of Forest Science
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• v.110 no.3
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• pp.453-461
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• 2021

The energy use of forest biomass is crucial to deal with climate change and achieve the carbon-neutral goal. This study aims to analyze the economic feasibility of forest biomass thermal energy facilities and calculate the optimal subsidy level of heat supply to ensure continued operation of the facilities. To achieve this aim, the net present value approach (NPV) and call option price model are adopted considering wood chip price volatilities. The Forest Energy Self-Sufficient Village Project financed by Korea Forest Service is considered as the research case study. In our analysis, when 50% of the initial investment is given to the subsidies and RECs are applied to only power generation, NPV and IRR are both negative and the investment value using the real option model is also zero. We concluded that some heat subsidies should be acknowledged to keep the facilities operating. Besides, the simulation results reveal reliable economic values when the heating subsidy is priced at KRW 0.0248 per kcal.

• Animal Bioscience
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• v.34 no.5
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• pp.789-800
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• 2021

Objective: Conservation and genetic improvement of cattle breeds require information about genetic diversity and population structure of the cattle. In this study, we investigated the genetic diversity and population structure of the three cattle breeds in the Korean peninsula. Methods: Jeju Black, Hanwoo, Holstein cattle in Korea, together with six foreign breeds were examined. Genetic diversity within the cattle breeds was analyzed with minor allele frequency (MAF), observed and expected heterozygosity (HO and HE), inbreeding coefficient (FIS) and past effective population size. Molecular variance and population structure between the nine breeds were analyzed using a model-based clustering method. Genetic distances between breeds were evaluated with Nei's genetic distance and Weir and Cockerham's FST. Results: Our results revealed that Jeju Black cattle had lowest level of heterozygosity (HE = 0.21) among the studied taurine breeds, and an average MAF of 0.16. The level of inbreeding was -0.076 for Jeju Black, while -0.018 to -0.118 for the other breeds. Principle component analysis and neighbor-joining tree showed a clear separation of Jeju Black cattle from other local (Hanwoo and Japanese cattle) and taurine/indicine cattle breeds in evolutionary process, and a distinct pattern of admixture of Jeju Black cattle having no clustering with other studied populations. The FST value between Jeju Black cattle and Hanwoo was 0.106, which was lowest across the pair of breeds ranging from 0.161 to 0.274, indicating some degree of genetic closeness of Jeju Black cattle with Hanwoo. The past effective population size of Jeju Black cattle was very small, i.e. 38 in 13 generation ago, whereas 209 for Hanwoo. Conclusion: This study indicates genetic uniqueness of Jeju Black cattle. However, a small effective population size of Jeju Black cattle indicates the requirement for an implementation of a sustainable breeding policy to increase the population for genetic improvement and future conservation.