Journal of Convergence for Information Technology (융합정보논문지)

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5-bit FLASH A/D Converter Employing Time-interpolation Technique

시간-보간법을 활용한 5-bit FLASH ADC

  • Nam, Jae-Won (Department of Electronic and IT Media Engineering, SeoulTech) ;
  • Cho, Young-Kyun (Division of Electrical, Electronic and Control Engineering, Kongju National University)
  • 남재원 (서울과학기술대학교 전자IT미디어공학과) ;
  • 조영균 (공주대학교 전기전자제어공학부)
  • Received : 2021.07.20
  • Accepted : 2021.09.20
  • Published : 2021.09.28
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Abstract

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

본 연구는 시간-보간법을 적용한 FLASH analog-to-digital converter (ADC)에 관한 것이다. 시간-보간법은 기존의 FLASH ADC에서 요구되는 전압영역 비교기의 개수를 줄일 수 있으며 이 따른 전력 소모 및 칩 면적의 절약을 기대할 수 있다. 본 연구에서는 5-bit, 즉 31개의 양자화 레벨을 갖는 ADC를 설계 및 구현하였으며, 16개의 양자화 레벨은 기존의 전압영역 비교기 방식을 유지하고, 나머지 15개의 양자화 레벨은 시간영역 비교기를 통하여 처리되도록 구성하여, 기존 5-bit FLASH ADC 대비 전압영역 비교기의 숫자를 48.4% 줄일 수 있었다. 시제품은 14 nm Fin Field-effect transistor (FinFET) 공정으로 제작되었으며 구현면적은 0.0024 mm2, 전력소모는 0.8 V 전원전압에서 0.82 mW로 측정되었으며, 400 MS/s의 변환속도 21 MHz 정현파 입력에 대하여 ADC는 28.03 dB의 신호-대-잡음비 (SNDR), 즉 4.36 유효비트(ENOB)의 성능을 보였다.

Keywords

Acknowledgement

This study was supported by the Research Program funded by the SeoulTech(Seoul National University of Science and Technology).

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