• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1016-1021
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• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.6
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• pp.556-563
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• 2007

The current trend of low cost ultra-small satellites is to utilize Commercial Off the Shelf (COTS) parts to save cost, and accordingly, Command and Data Handling (C&DH) that operates the satellite and collects/processes the data is also designed and developed around commercial controllers. However, functionalities of commercial controllers are limited according to the specs outlined by the manufacturer. In order for the commercial controllers to be used for satellites where variety of interfaces is required, a separate interface circuit is required. Therefore, a Multi Digital Data Control System (MDDCS) using Field Programmable Gate Array (FPGA) has been developed in order to expand multiple digital interfaces that are not supported by the commercial controller, and also to compensate for SEU. This has been implemented on Actel A3P1000 using Very High Speed Integrated Circuits Hardware Description Language (VHDL).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.393-394
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• 2018

In this paper, the new system which improve the previously reported "Implementation to human-computer interface system with motion tracking using OpenCV and FPGA" is introduced and in this system, a character selection system for the physically uncomfortable patients is proposed. Using OpenCV, the eye area is detected, the pupil position is determined, and then the results are sent to the FPGA, and the character is selected finally. The method to minimize the pupil movement of the patient is used to output the character according to the user's intention. Using OpenCV, various computer vision algorithms can be easily applied, and using programmable FPGA, a pupil motion recognition and character selection system are implemented with a low cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1259-1265
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• 2006

In this paper, we propose a combined synthetic algorithm of the logic level for high speed FPGA design. The algorithm divides critical path to reduce delay time and generates a circuit which the divided circuits execute simultaneously. This kernel selection algorithm is made by C-langage of SUN UNIX. We compare this with the existing FlowMap algorithm. This proposed algorithm shows result on 33.3% reduction of delay time by comparison with the existing algorithm.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.23-26
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• 2022

In this paper, our ray tracing hardware is implemented on the latest high-capacity FPGA board. The system included ray tracing hardware for rendering and tree building hardware for handling dynamic scenes. The FPGA board used in the implementation is a Xilinx Alveo U250 accelerator card for data centers. This included 12 ray tracing hardware cores and 1 tree-building hardware core. As a result of testing in various scenes in Full HD resolution, the FPS performance of the proposed ray tracing system was measured from 8 to 28. The overall average is about 17.7 FPS.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.12-18
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• 1997

An efficient synthesis method of cellular architecture FPgA is proposed in this paper. To generate a logical representation called complex term which is to be directly mapped onto the cellular architecture FPGA, and SO or ESOP minimization tool was used in previous methods. Instead, we use a logic function transformed into BDD (binary decision diagram) in the actual generation of the complex temrs. In this process it estimates the cost(i.e. the number of complex terms) for three branches, 0-branch and 1-branches. This process is continued over the whole BDD to do such computation, and we observed that the number of complex terms has been reduced compared to the previous results.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.4
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• pp.123-134
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• 2004

In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.225-227
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• 2008

This paper deals with the implementation on a Field Programmable Gate Array (FPGA) of PWM switching patterns for a voltage multilevel inverter. The reference data in main microcontroller is transmitted to the FPGA through 16 general purpose I/O ports. Herein, three-phase reference voltage signals are addressed by the last 2-bit (bit 15-14) and their data are assigned in remaining 14-bit, respectively. The carrier signals are created by 16-bit counter in up-down counting mode inside FPGA according to desirable topology. Each reference signal is compared with all carrier signals to generate corresponding PWM switching patterns for control of the multilevel inverter. Useful advantages of this scheme are easy implementation, simple software control and flexibility in adaptation to produce many PWM signals. Some simulations and experiments are carried out to validate the proposed method.