• Journal of the Korea Society of Computer and Information
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• v.14 no.11
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• pp.97-103
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• 2009

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.

• Journal of Aerospace System Engineering
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• v.16 no.4
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• pp.10-16
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• 2022

Since aviation systems are developed as the complex form of software a hardware, the necessity to apply to relevant guidelines is increasing. It is however uncommon that international development guidelines regarding electronic hardware are applied to current domestic aviation systems. In this paper, we compare and analyze DO-254 and ECSS-Q-ST-60-02C, electronic hardware development guidelines with the case of KASS (Korea Augmentation Satellite System) Performance Suitability, based on the project of SBAS (Satellite Based Augmentation System) development and construction.

• Journal of Korea Multimedia Society
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• v.10 no.11
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• pp.1460-1471
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• 2007

A 3-Dimensional engine in a mobile embedded device is divided into a C-based OpenGL/ES and a Java-based JSR184 which interprets and executes a byte code in a real-time. In these two standards, the JSR184 supporting Java objects uses more processor resources than an OpenGL/ES and thus has a constraint when it is used in an embedded device with a limited computing power. On the other hand, 3-Dimensional contents employed in existing personal computer are created by utilizing advantages of Java and secured numerous users in European market, due to the good quality in contents and extensive service in a commercial network, GSM. Because of the reason, a mobile embedded device used in a GSM network needs a JSR184 which can provide an existing Java-based 3-Dimensional contents without extra conversion processes, but the current version of Java-based 3-Dimensional engine has drawbacks in application to commercial products because it requires more computing power than the mobile embedded device. This paper proposes a binding technique with the advantages of Java objects to improve a processing speed of 3-Dimensional contents in limited resources of a mobile embedded device. The technique supports a JSR184 standard interface in the upper layer to utilize 3-Dimensional contents using Java, employs a different code-conversion language, KNI(Kilo Native Interface), in the middle layer to interface between OpenGL/ES and JSR184, and embodies an OpenGL/ES standard in the lower layer. The validity of the binding technique is demonstrated through a simulator and a FPGA embedding an ARM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3C
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• pp.398-407
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• 2004

In this paper, a blind watermarking method which is suitable to the video compression using 2-D discrete wavelet transform was proposed and implemented into the hardware using VHDL(VHSIC Hardware Description Language). The goal of the proposed watermarking algorithm is the authentication about the manipulation of the watermark embedded image and the detection of the error positions. Considering the compressed video image, the proposed watermarking scheme is unrelated to the quantization and is able to concurrently embed or extract the watermark. We experimentally verified that the lowest frequency subband(LL4) is not sensitive to the change in the spatial domain, so LL4 subband was selected for the mark space. And the combination of the bitplanes which has the properties of both the minimum degradation of the image and the robustness was chosen as the embedded Point in the mark space in LL4 subband. Since we know the watermark embedded positions and the watermark is embedded by not varying the value but changing the value, the watermark can be extracted without the original image. Also, for the security when exposing the watermark embedded position, we embed the encrypted watermark by the block cipher. The proposed watermark algorithm shows the robustness against the general image manipulation and is easily transplanted into the image or video compressor with the minimal changing in the structure. The designed hardware has 4037 LABs(24％) and 85 ESBs(3％) in APEX20KC EP20K400CF672C7 FPGA of Altera and stably operates in 82MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.2
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• pp.196-201
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• 2013

In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

• Publications of The Korean Astronomical Society
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• v.21 no.2
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• pp.67-74
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• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.8
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• pp.30-38
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• 2011

This paper proposes a new intelligent diagnosis equipment for the partial discharge, which keeps deteriorating the insulating materials inside electric machineries, ultimately leading to electrical breakdown. In order to simulate experimentally the partial discharge inside the electric machinery, the tip-to-plate, the sphere-to-plate, the sphere-to-sphere and the plate-to-plate electrodes are used respectively, of which the gaps are 1[mm], 3[mm] or 5[mm] and the applied voltages are 3[kV], 5[kV] or 7[kV]. Ceramic coupler sensor and FIR digital filter are used to measure the partial discharge and the artificial neural network is used for the deterioration diagnosis of the electric machinery. The microprocessor of PD diagnosis equipment is DSP (TMS320C6713) with FPGA (Cyclone II). The results of the real-time and on-line experiments performed with the developed equipment are also explained.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3C
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• pp.264-270
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• 2006

In this paper, we propose the modified display color control system using white point line, boundary lines and S-shaped curves to emphasize blue and red tone colors on CIE1931 diagram. The proposed system divides RGB gamut into movable area and non-movable area by using boundary lines. The colors in movable area are moved into right side or left side along quadratic curve to change the bluish (or reddish) color to more bluish (or more reddish), while those in non-movable area are excepted from color control to prevent skin color from changing. The loci of the quadratic curves are very similar to the arc of the white-point line which connects all points that represent the chromaticities of a black body radiator at different temperatures and is also called the black body locus. The RGB gamut extension by movement of chromaticity coordinate can improve color reproducibility. Therefore in the case of application to LCD, the display shows excellent performance because the LCD's color reproducibility is comparatively lower than that of other display systems. The proposed system is also experimentally demonstrated with Xilinx Virtex FPGA XCV2000E- 6BG560 and the TV set.

• ETRI Journal
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• v.33 no.3
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• pp.382-392
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• 2011

This paper proposes the streaming radio frequency identification (RFID) protocol to support robust data streaming in a passive communication, which is extended from the ISO18000-6 Type C RFID standard. By observing and modeling the unique bit error behavior through detailed analysis in this paper, we found that performance is significantly limited by inaccurate and unstable link frequencies as well as low SNR which are inevitable for passive devices. Based on the analysis, we propose a simple and efficient protocol to adaptively insert extra error control sequences in a packet for tolerating tough link condition while maximizing the throughput and preserving the minimal implementation cost. To evaluate effectiveness of our proposal in real-time streaming applications, we experimented on real-time H.264 video streaming and prototyped the system on FPGA. To our best knowledge, our paper is the first work to take analytical approach for maximizing the throughput and demonstrate the possibility of the realtime multimedia streaming transmission in the passive RFID system.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.289-291
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• 2007

The Digital Multimedia Broadcasting(DMB) system is developed to offer high quality audio-visual multimedia contents to the uses by the various portable terminals in the mobile environment. Integrated complex reception platform is required to receive multimedia broadcasting services transmitted from various transmission media. In this paper, we present the design and implementation technic for providing the both of terrestrial and satellite DMB services simultaneously using the same hardware platform. The implemented complex receiving terminal to accommodate these DMB services simultaneously need composed of it RF module. it baseband module, it complex control module and the complex de-multiplexer module. The complex control module is designed using uClinux operating system. The complex de-multiplexer, which perform the functions of the address decoder and each DMB stream de-multiplexer, is implemented. with FPGA device. The implemented platform is tested in a real environment and its performance is satisfied with required performance criteria.