• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.8-18
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• 1997

In FPGAs, we may use the property of the routing architecture for their routing compared to the routing in the conventional layout style. Especially, the Xilinx XC4000 series FPGAs have very special routing architecture in which the routing problem is equivalent to the two dimensional track assignment problem. In this paper, we propose a new FPgA detailed routing method by developing a two dimensional trackassigment heuristic algorithm. The proposed routing mehtod accept a global routing result as an input and obtain a detailed routing such that the number of necessary wire segments in each connection block is minimized. For all benchmark circuits tested, our routing methd complete routing results. The number of used tracks are also similar to the results by thedirect routing methods.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.117-123
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• 2012

This paper implements mobile Worldwide Interoperability for Microwave Access (WiMAX) receiver using Software Defined Radio (SDR) technology. SDR system is difficult to implement on the mobile handset because of restrictions that are computing power and under space constraints. The implemented receiver processes mobile WiMAX software modem on Open Multimedia Application Platform (OMAP) System on Chip (SoC) and Field Programmable Gate Array (FPGA). OMAP SoC is composed of ARM processor and Digital Signal Processor (DSP). ARM processor supports Single Instruction Multiple Data (SIMD) instruction which could operate on a vector of data with a single instruction and DSP is powerful image and video accelerators. For this reason, we suggest the possibility of SDR technology in the mobile handset. In order to verify the performance of the mobile WiMAX receiver, we measure the software modem runtime respectively. The experimental results show that the proposed receiver is able to do real-time signal processing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.182-192
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• 2010

This paper proposes the hardware IP design of JBIG2 encoder. In order to facilitate the next generation FAX after the standardization of JBIG2, major modules of JBIG2 encoder are designed and implemented, such as symbol extraction module, Huffman coder, MMR coder, and MQ coder. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the synthesis of VHDL code. To minimize the memory usage, 128 lines of input image are processed succesively instead of total image. The synthesized IPs are downloaded to Virtex-4 FX60 FPGA on ML410 development board. The four synthesized IPs utilize 36.7% of total slice of FPGA. Using Active-HDL tool, the generated IPs were verified showing normal operation. Compared with the software operation using microblaze cpu on ML410 board, the synthesized IPs are better in operation time. The improvement ratio of operation time between the synthesized IP and software is 17 times in case of symbol extraction IP, and 10 times in Huffman coder IP. MMR coder IP shows 6 times faster and MQ coder IP shows 2.2 times faster than software only operation. The synthesized H/W IP and S/W module cooperated to succeed in compressing the CCITT standard document.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.33-39
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• 2018

In this paper, We studied the possibility of SoC(System On Chip) design using infrared image processing IP(Intellectual Property). And, we studied NUC(Non Uniformity Correction), BPR(Bad Pixel Recovery), and CEM(Contrast Enhancement) processing, the infrared image processing algorithm implemented by IP. We showed the logic and timing diagram implemented through the hardware block designed based on each algorithm. Each algorithm was coded as RTL(Register Transfer Level) using Verilog HDL(Hardware Description Language), ALTERA QUARTUS synthesis, and programed in FPGA(Field Programmable Gated Array). In addition, we have verified that the image data is processed at each algorithm without any problems by integrating the infrared image processing algorithm. Particularly, using the directly manufactured electronic board, Processor, SRAM, and FLASH are interconnected and tested and the verification result is presented so that the SoC type can be realized later. The infrared image processing IP proposed and verified in this study is expected to be of high value in the future SoC semiconductor fabrication. In addition, we have laid the basis for future application in the camera SoC industry.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.175-182
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• 2011

In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.38-49
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• 2006

In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.966-973
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• 2000

In this paper, we propose a novel RS decoder design yielding smallr circuit size shorter coding latency. The proposed architecture of RS decoder has the following two features. First, circuit size reduced by using Euclid algorithm with mutual operation between cells. Second, coding latency is reduced by using higher frequency than syndrome and error value calculation block. We performed simulation with C language and MATLAB in order to verify the decoding algorithm and implemented using FPGA chips in VHDL.