• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.63-69
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• 2017

This paper presents a highly efficient power management system for UAV-drones. For free from the battery cell-balancing issue, the proposed system allows the drone to utilize a single-cell Li-Po battery. To realize low-voltage input of 3.7V, the switch-mode step-up DC-DC converter is optimally designed with high power efficiency. The prototype DC-DC converter was implemented with an output voltage of 5V, which will be provided to digital parts of the drone. The power efficiency was measured to be max. 91.3% with low surface temperature. The measured line and load regulations were 0.02V/V and 0.15V/A, respectively. Thanks to the proposed power management system, the available time-to-fly of the drone is expected to be significantly extended in virtue of the enhanced power efficiency.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.534-537
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• 2001

This paper deals with the active clamp ZVS flyback converter for RF generator. The proposed converter has the characteristics of the low switching noise and high efficient regarding conventional flyback converter. To verify validity of the proposed converter, the 100kHz, 48V, 300W converter are simulation and experimental result. This converter will be apply to the discharge drive circuit for PDP(Plasma Display Panel) TV.

• Transactions on Electrical and Electronic Materials
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• v.5 no.2
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• pp.71-75
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• 2004

This paper proposes a new bandgap reference (BGR) circuit which takes advantage of a cascode current mirror biasing to reduce the V$\_$ref/ variation, and sizing technique, which utilizes two related ratio numbers k and N, to reduce the PNP BJT area. The proposed BGR is designed and fabricated on a test chip with a goal to provide a reference voltage to the 10 bit A/D(4-4-4 pipeline architecture) converter of the CMOS Active Pixel Sensor (APS) imager to be used in X-ray imaging. The basic temperature variation effect on V$\_$ref/ of the BGR has a maximum delta of 6 mV over the temperature range of 25$^{\circ}C$ to 70$^{\circ}C$. To verify that the proposed BGR has radiation hardness for the X-ray imaging application, total ionization dose (TID) effect under Co-60 exposure conditions has been evaluated. The measured V$\_$ref/ variation under the radiation condition has a maximum delta of 33 mV over the range of 0 krad to 100 krad. For the given voltage, temperature, and radiation, the BGR has been satisfied well within the requirement of the target 10 bit A/D converter.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.358-361
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• 2002

The millirneterwave high-T$_{c}$ superconducting(HTS) down-converter sub-system with the HTS/III-V integrated mixer as the central device is demonstrated first. The constituent components of HTS down-converter sub-system such as a single balanced type integrated mixer with rat-race coupler, a cavity type bandpass filter (26 GHz), and a HTS planar lowpass filter(1 GHz), semiconductor LNA and IF-power amplifier, a driving electronic module for A/D converter, and a Stirling type mini-cooler module were combined into an International stand- and rack of 19-inch. From the RF(-61 dBm, 26.5GHz)and LO signal(-1 dBm, 25.6 GHz), IF signal(0dBm, 0.9 GHz) agreed with simulated results is obtained.d.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3114-3116
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• 2005

The AC-DC converter, which has three-phase AC power as input and isolated DC power as output is used for the regulated DC power supply of the telecommunication power processing system for several kilowatt class applications. The conventional DC power supply for the telecommunication power system comprises a PWM rectifier with sine-wave shaping input current unity power factor and a DC/DC converter connected to the PWM converter, which obtains DC 48[V]. Since power passes through these two power stage converters, the conversion power loss is difficult to provide high efficiency. To resolve these problems, this paper presents a new PWM rectified as a 1-stage power conversion method. It simulation and experimental results as proved from a practical point of view that 92.1[%] of conversion efficiency and input current which can meet harmonics regulation of the Class-A in IEC61000-3-3 are achieved.

• Journal of the Korean Society of Industry Convergence
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• v.21 no.6
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• pp.265-271
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• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

• Proceedings of the IEEK Conference
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• summer
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• pp.66-69
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• 2004

This work is the study of Voltage-Down Converter used as internal supply voltage having large current driving and stable voltage level at any variation of process, voltage, and temperature(P.V.T). It converts VDD(external supply voltage) into $V_{1NT}(internal\;supply\;voltage).$ From the simulation results, a new Voltage-Down Converter has large current driving and a little stand-by current under lower supply voltage than conventional circuit. And bad characteristic of VINT, peaking, was eliminated. Start-up circuit for BGR is also added to one circuit, which consumes less current dissipation than convention circuit

• Journal of Power Electronics
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• v.8 no.1
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• pp.60-73
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• 2008

In this paper a three-phase ac-to-dc resonant converter with high input power factor and isolated output is proposed. To improve the input power factor of the converter, high frequency current is injected into the input of the three-phase diode bridge rectifier. It is injected through an impedance network consisting of a series of L-C branches from the output of the high frequency three-phase inverter. A narrow switching frequency variation is required to regulate the output voltage. A design example with different design curves is illustrated along with the component ratings. Experimental verification of the converter is performed on a prototype of 3 kW, 1000 V output, operating above 300 kHz. Experimental results confirm the concept of the proposed converter. Narrow switching frequency variation is required to regulate the output voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.448-451
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• 2011

SoC에서 칩 내부의 온도를 측정하기 위한 proportional-to-absolute-temperature (PTAT) 회로와 sensing 된 아날로그 신호를 디지털로 변환하기 위해 4-bit analog-to-digital converter (ADC)로 구성된 temperature sensor를 제안한다. CMOS 공정에서 vertical PNP 구조를 이용하여 PTAT 회로가 설계되었다. 온도변화에 둔감한 ADC를 구현하기 위해 아날로그 회로를 최소로 사용하는 successive approximation (SA) ADC가 이용되었다. 4-bit SA ADC는 capacitor DAC와 time-domain 비교기를 이용함으로 전력소모를 최소화하였다. 제안된 temperature sensor는 2.5V $0.25{\mu}m$ 1-poly 9-metal CMOS 공정을 이용하여 설계되었고, $50{\sim}150^{\circ}C$ 온도 범위에서 동작한다. Temperature sensor의 면적과 전력 소모는 각각 $130{\times}390\;um^2$과 868 uW이다.