• Journal of Institute of Control, Robotics and Systems
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• v.16 no.6
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• pp.559-565
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• 2010

In this paper, we present a transformation method of source code from a POSIX (Portable Operating System Interface) based source code into an OSEK/VDX (Offene Systeme und deren Schnittstellen fur die Elektronik in Kraftfahrzeugen/Vehicle Distributed eXecutive) source code. As the electronic parts of automobile systems increase, the use of embedded software in automobile systems is also growing. Accordingly, many electronic systems are designed in automobile system with OSEK/VDX. Otherwise, one of the major problems of embedded software would be portability to other OS's. To enhance the portability and interoperability of embedded software, we propose a source code transformation method from POSIX to OSEK/VDX based on API (Application Programming Interface) translation method. Considering the characteristics of the OSEK/VDX which uses OIL (OSEK/VDX Implementation Language) standard, transformation process is performed with source code transformation and OIL code generation. For the validity of the proposed method, the transformation experiment is given using Micro-C OS II and OSEK/VDX with XC167CI micro-controller.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7C
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• pp.587-593
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• 2010

In this paper we design an irregular low-density parity-check (LDPC) code for multiple-input multiple-output (MIMO) system, using a simple extrinsic information transfer (EXIT) chart method. The MIMO systems considered are optimal maximum a posteriori probability (MAP) detector. The MIMO detector and the LDPC decoder exchange soft information and form a turbo iterative receiver. The EXIT charts are used to obtain the edge degree distribution of the irregular LDPC code which is optimized for the MIMO detector. It is shown that the performance of the designed LDPC code is better than that of conventional LDPC code which was optimized for either the Additive White Gaussian Noise (AWGN) channel or the MIMO channel.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.169-172
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• 2015

Dalvik is a virtual machine (VM) that is designed to run Java-based Android applications. A trace-based just-in-time (JIT) compilation technique is currently employed to improve performance of the Dalvik VM. However, due to runtime compilation overhead, the trace-based JIT compiler provides only a few simple optimizations. Moreover, because each trace contains only a few instructions, the trace-based JIT compiler inherently exploits fewer optimization and parallelization opportunities than a method-based JIT compiler that compiles method-by-method. So we propose a new method-based JIT compiler, named DEX2C, in order to improve performance by finding more opportunities for both optimization and parallelization in Android applications. We employ C code as an intermediate product in order to find more optimization opportunities by using the GNU C Compiler (GCC), and we will detect parallelism by using the Intel C/C++ parallel compiler and the AESOP compiler in our future work. In this paper, we introduce our DEX2C compiler, which dynamically translates Dalvik bytecodes (DEX) into C code with method granularity. We also describe a new method-based JIT interface in the Dalvik VM for the DEX2C compiler. Our experiment results show that our compiler and its interface achieve significant performance improvement by up to 15.2 times and 3.7 times on average, in Element Benchmark, and up to 2.8 times for FFT in Smartbench.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.161-172
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• 2000

In this paper, we introduce the development of a LOTOS-based tool, supporting formal methods, called ForTIA (A Formalism for Telecommunication and Information Systems). By using LOTOS, an ISO standard formal specification language, the user requirements and system models can be abstracted and represented formally. Therefore, the system can be validated and verified on the specifications, before implementations. ForTIA supports light-weight formal methods based on validation to be used in real industry. Key functions of ForTIA are simulation and C++ code generation. In simulation, tree based visual validation mechanism is provided and in code generation, the full C++ source code is generated to be used for system implementations.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.4
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• pp.335-342
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• 2021

By using HLS when developing a communication system FPGA, HDL code can be automatically generated from a little modified C/C++ source code used for performance verification, which has the advantage of shortening the development period. In this paper, a method of designing a telemetry standard 106-17 LDPC decoder in C language is proposed using Xilinx's Vivado HLS, and by synthesizing Spartan-7 and Kintex-7 as target devices, throughput and FPGA utilization rate was compared.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.69-76
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• 2005

In this paper, we propose a biorthogonal modulation employing a constant-amplitude transmission of multi-code signals by introducing a simple constant-amplitude coding scheme with redundant bits. The proposed constant-amplitude biorthogonal multi-code (CABM) modulation can provide high spectral efficiency compared with a conventional direct sequence/spread spectrum (DS/SS) modulation. Nevertheless the proposed CABM modulation can keep up a constant-amplitude signal. Additionally, we propose various types of demodulation structures for the CABM modulation. Simulation results show that bit error rate (BER) performance and hardware complexity of the proposed CABM modulation are highly improved in comparison with those of a constant-amplitude orthogonal multi-code (CAOM) modulation.

• International journal of advanced smart convergence
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• v.6 no.1
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• pp.1-8
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• 2017

Diverse types of malicious code such as evasive Server-side Polymorphic are developed and distributed in third party open markets. The suspicious new type of polymorphic malware has the ability to actively change and morph its internal data dynamically. As a result, it is very hard to detect this type of suspicious transaction as an evidence of Server-side polymorphic mobile malware because its C&C server was shut downed or an IP address of remote controlling C&C server was changed irregularly. Therefore, we implemented Simulated C&C Server to aggregate activated events perfectly from various Server-side polymorphic mobile malware. Using proposed Simulated C&C Server, we can proof completely and classify veiled server-side polymorphic malicious code more clearly.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.20-28
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• 1997

In this paper, quantization and inverse quantizatio unit, a sa component of MPEG-2 moving picture compression system, ar edesigned. In the processing of quantization, this design adopted newly designed arithmetic units in which quantization matrices and scale code was expressed with SD(signed-digit) code. In the arithmetic unit of inverse quantization, quantization scale code, which has 5-bits length, is splited into two pieces; 2-bits for control code, 3-bits for quantization data, and the method to devise quantization step size is proposed. The design was coded with VHDL and synthesis results in that it consumed about 6,110 gates, and operating speed is 52MHz.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.587-590
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• 1988

In the case of VLSI computer system control unit design using PLA, optimal state code assignment algorithm to minimize the PLA area is proposed. An optimal state code assignment algorithm which considers output state and logic minimization simultaneously is proposed, and by means of this, algorithm product term is minimized. Also, by means of this algorithm running time and memory capacitance is decreased as against heuristic state code assignment algorithm which uses matrix calculation and considers the constraint relation only. This algorithm is implemented on VAX 11/750 (UNIX4.3BSD). Through the various test example applied proposed algorithm, the efficiency of this algorithm is shown.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.831-845
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• 1997

In this paper,we proposed and developed a compiler and interactive programming enviroments for C++ wich is mostly worth of nitice among the object -oriented languages.To develope the compiler for C++ we took front=end/back-end model using EM virtual machine.In develpoing Front-End,we formailized C++ gram-mar with the context semsitive tokens which must be manipulated by dexical scanner and designed a AST class li-brary which is the hierarchy of AST node class and well defined interface among them,In develpoing Bacik-End,we proposed model for three major components :code oprtimizer,code generator and run-time enviroments.We emphasized the retargatable back-end which can be systrmatically reconfigured to genrate code for a variety of distinct target computers.We also developed terr pattern matching algorithm and implemented target code gen-erator which produce SPARC code.We also proposed the theroy and model for construction interative pro-gramming enviroments. To represent language features we adopt AST as internal reprsentation and propose uncremental analysis algorithm and viseal digrams.We also studied unparsing scheme, visual diagram,graphical user interface to generate interactive environments automatically Results of our resarch will be very useful for developing a complier and programming environments, and also can be used in compilers for parallel and distributed enviroments.