• Journal of information and communication convergence engineering
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• 제9권4호
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• pp.428-430
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• 2011

Recent semiconductor design technology has been substantially developed that we can design a micro-system on a chip as well as implementing an application specific IC in an FPGA. SPARTAN-3E developed by Xilinx is equipped with an FPGA that holds as much as 500 thousand transistors connected with MicroBlaze softcore microprocessor bus system. In this paper, we discuss a method of implementing an embedded system using the SPARTAN-3E. We also explain the peripherals and the bus protocols and the expandability of this kind of embedded systems.

• Journal of information and communication convergence engineering
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• 제15권4호
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• pp.237-243
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• 2017

This paper presents an analysis of the electromagnetic interference of a heterogeneous power bus where electromagnetic bandgap (EBG) cells are irregularly arranged. To mitigate electrical-noise coupling between high-speed circuits, the EBG structure is placed between parallel plate waveguide (PPW)-based power buses on which the noise source and victim circuits are mounted. We examine a noise suppression characteristic of the heterogeneous power bus in terms of scattering parameters. The characteristics of the dispersion and scattering parameters are compared in the sensitivity analysis of the EBG structure. Electric field distributions at significant frequencies are thoroughly examined using electromagnetic simulation based on a finite element method (FEM). The noise suppression characteristics of the heterogeneous power bus are demonstrated experimentally. The heterogeneous power bus achieves significant reduction of electrical-noise coupling compared to the homogeneous power buses that are adopted in conventional high-speed circuit design. In addition, the measurements show good agreement with the FEM simulation results.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.535-536
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• 2006

In the embedded system, external device interface that operates serial protocol with lower speed than the general computers is used commonly. This paper describes I2C bus protocol that is a bi-directional serial bus with a two-pin interface. The I2C bus requires a minimum amount of hardware to relay status and reliability information concerning the processor subsystem to an external device.

• Journal of the Korean Institute of Telematics and Electronics B
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• 제33B권9호
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• pp.70-79
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• 1996

Block data transfer poses a serious problem is a pipelined bus where each data transfer step is pipelined. In this paper, we describe the design and implementation of a variable data block transfer protocol for a pipelined bus of a shared-memory multiprocessor. The proposed method maintains compatibility with the existing protocol for the pipelined bus and ensures fairness and effectiveness by preventing starvation. We present flow charts of requester and responder during a block transfer in the pipelined bus that uses the proposed protocol. The proposed protocol was implemented for the TICOM-III HiPi+Bus.

• Proceedings of the KSME Conference
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• 대한기계학회 2003년도 추계학술대회
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• pp.169-174
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• 2003

The thermal design of the bus bar of a Gas-Insulated Switchgear(GIS) becomes important since the current-carrying capacity of the GIS is limited by maximum operating temperature. In order to predict temperature rise of the bus bar, a program has been developed. Various heat sources possibly generated in the bus bar are calculated in the program. To estimate temperature rises at the bus bar caused by the heat balance between the heat generation and heat transfer, the finite volume method as well as the $4^{th}$ order Runge-Kutta method has been employed. In the experiments, temperature rises at conductor, contact part and external tank are measured for full-scale gas-insulated bus bars. The comparisons of the predicted values of the heat balance calculation to those of the experiments are made. From the comparisons, it is concluded that the developed program can predict the temperature rise of the bus bar quite well.

• Journal of KIISE:Computer Systems and Theory
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• 제29권12호
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• pp.680-686
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• 2002

In deep-submicron (BSM) design, coupling effects between wires on the bus cause serious problems such as crosstalk delay, noise, and power consumption. Most of the previous works on bus encoding are targeted either to minimize tile power consumption on bus or to minimize the crosstalk delay, but not both. In this paper, we propose a new bus encoding algorithm that minimizes the power consumption on bus and eliminates the crosstalk delay simultaneously. We formulate and solve the problem by minimizing a weighted sum of the self transition and cross-coupled transition activities on bus From experiments using a set of benchmark designs. it is shown that the proposed encoding technique consumes at least 15% less power over the existing techniques, while completely eliminating the crosstalk delay.

• Smart Structures and Systems
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• 제24권4호
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• pp.427-434
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• 2019

This study investigates the structural integrity of the amphibious tour bus under the rollover condition. The multi-purpose bus called Dual Mode Tour Bus (DMTB) which explores on land and water has been designed on top of a truck platform. Prior to the fabrication of new upper body and sailing equipment of DMTB, computational analysis investigates the rollover protection of the proposed structure including superstructure, wheels, and axles. The Computer-Aided Design (CAD) of the whole vehicle model is meshed and preprocessed under high performance using the Altair HyperMesh to attain the best mesh model suited for finite element analysis (FEA) on the proposed system. Meanwhile, the numerical model is analyzed by employing LS-DYNA to evaluate the superstructure strength. The numerical model includes detail information about the microstructure and considers wheels and axles as rigid bodies but excludes window glasses, seats, and interior parts. Based on the simulation analysis and proper modifications especially on the rear portion of the bus, the local stiffness significantly increased. The vehicle is rotated to the contact point on the ground based on the mathematical method presented in this study to save computational cost. The results show that the proposed method of rollover analysis is highly significant not only in bus rollover tests but in crashworthiness studies for other application. The critical impartments in our suggested dual-purpose bus accepted and passed "Economic Commission for Europe (ECE) R66".

• Journal of Korea Society of Industrial Information Systems
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• 제23권6호
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• pp.39-46
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• 2018

Low-floor buses service in Korea has been spreading nationwide for transportation users with wheelchair since 2004. However, there is a lot of difficulty in using this information because the low-floor bus information is insufficient. Therefore, it is necessary to improve the service of using low-floor buses for the transportation weak in order to increase the usage rate of low-floor buses for those who use wheelchairs. In this paper, we designed and implemented a low-floor bus reservation system to provide low-floor bus service and low-floor bus reservation service to improve low-floor bus service of wheelchair users. The application of this system is expected to provide a better service to the transportation weak people using low - floor buses.

• Smart Media Journal
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• 제1권1호
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• pp.27-35
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• 2012

In this paper, the performance analysis for multimedia video codec(MPEG-4, H.264) on on-chip network communication architecture is presented. The On-Chip Network (OCN) is the new communication architecture of multimedia SoC design that overcomes the limits of On-Chip Bus architecture by providing higher data traffic bandwidth, reusability and higher scalability. We compared the performance of MPEG-4, H.264 decoder based on-chip network and AMBA on-chip bus. Experimental results show that the performance of MPEG-4, H.264 based on on-chip network is improved over 33~56% compared to the design based on AMBA on-chip bus.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제34C권3호
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• pp.1-10
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• 1997

We present an approach to high-level synthesis for a specific target architecture-partitioned bus architecture. In this approach, we have specific goals of minimizing data transfer length and number of buses in addition to common synthesis goals such as minimizing number of control steps and satisfying given resource constraint. Minimizing data transfer length and number of buses can be very important design goals in the era of deep submicron technology in which interconnection delay and area dominate total delay and area of the chip to be designed. in partitioned bus architecture, to get optimal solution satisfying all the goals, partitioning of operation nodes among segments and ordering of segments as well as scheduling and allocation/binding must be considered concurrently. Those additional goals may impose much more complexity on the existing high-level synthesis problem. To cope with this increased complexity and get reasonable results, we have employed two ideas in ur synthesis approach-extension of the target architecture to alleviate bus requirement for data transfer and adoption of genetic algorithm as a principal methodology for design space exploration. Experimental results show that our approach is a promising high-level synthesis mehtodology for partitioned bus architecture.