• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.24-31
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• 2003

Short channel effects (SCE) of bulk MOSFET with super-steep retrograded channels (SSR), fully-depleted SOI, and double-gate MOSFET have been analyzed using a evanescent-mode analysis. Analytical equations of the characteristics scaling-length (λ) for three structures have been derived and the accuracy of the calculated λ was verified by comparing to the device simulation result. It is found that the minimum channel length should be larger than 5λ and the depletion thickness of the SSR should be around 30 nm in order to be applicable to 70 nm CMOS technology. High-$textsc{k}$ dielectric shows a limitation in scaling due to the drain-field penetration through the dielectric unless the equivalent SiO2 thickness is very thin.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.21-27
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• 2009

In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.13-19
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• 2010

MOSFET with deuterium-incorporated gate oxide shows enhanced reliability compared to conventional MOSFET. We present an alternative process whereby deuterium is delivered to the location where the gate oxide reside by an implantation process. Deuterium ions were implanted using two different energies to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas was performed to remove the D-implantation damage. We have observed that deuterium ion implantation into the gate oxide region can successfully remove the interface states and the bulk defects. But the energy and the dose of the deuterium implant need to be optimized to maintain the Si substrates dopant activation, while generating deuterium bonds inside gate oxide. CV and IV characteristics studies also determined that the deuterium implant dose not degrade the transistor performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.15-22
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• 2008

The bulk-planer MOSFET has a scaling limitation due to the short channel effect (SCE). The Double-Gate MOSFET (DG-MOSFET) is a next generation device for nanoscale with excellent control of SCE. The quantum effect in lateral direction is important for subthreshold characteristics when the effective channel length of DG-MOSFET is less than 10nm, Also, ballistic transport is setting important. This study shows modeling and design issues of nanoscale DG-MOSFET considering the 2D quantum effect and ballistic transport. We have optimized device characteristics of DG-MOSFET using a proper value of $t_{si}$ underlap and lateral doping gradient.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.13-22
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• 2010

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET overcomes the limitation of bulk-MOSFET's channel controllability and enables to control the front and back-gate voltages independently. Therefore, circuit designs utilizing the IGM-DG MOSFETs provide the advantage of setting 4-terminal freely, hence achieving not only the performance improvement but also the larger scale integration. This paper presents a 15Gb/s optical receiver with a 1.0V power supply voltage, which consists of a transimpedance amplifier (TIA), a feedforward limiting amplifier (LA), and an output buffer. HSPICE simulations were conducted to confirm the circuit performance, and also to verify the circuit stability issues which may occur from the variations of process and supply voltage.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.5-8
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• 2002

Hot carrier induced device degradation is observed in thin-film, gate-all-around SOI transistor under DC stress conductions. We observed the more significant device degradation in GAA device than general single gate SOI device due to the degradation of edge transistor. Therefore, it is expected that the maximum available supply voltage of GAA transistor is lower than that o( bulk MOSFET or single gale SOI device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.9-14
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• 2012

In this study, multi-finger RF MOSFET substrate parameters are accurately extracted by using S-parameters measured from common source-bulk and common source-gate test structures. Using this extraction method, the accuracy of an asymmetrical model with three substrate resistances is verified by observing better agreement with measured Y-parameters than a simple model with a single substrate resistance. The modeled S-parameters of the asymmetrical model also show excellent agreement with measured ones up to 20GHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.170-173
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• 2003

In this paper, we proposed a new bulk LDMOS structure which can be used for RF application, and its fabrication steps were introduced. The simulated devices consist of three types: Bulk device, SLB(SOI Like Bulk), and SOI device. As a result of process and device simulation, we showed electrical characteristics, such as threshold voltage, subthreshold slope, DIBL(Drain Induced Barrier Lowering), off-state current, and breakdown voltage. In this simulation study, the lattice temperature model was adopted to see the device characteristics with lattice temperature during the operation. SLB device structure showed the best breakdown characteristics among the other structures. The breakdown voltage of SLB structure is about 9V, that of bulk is 7V, and that of SOI is 8V.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.5
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• pp.147-153
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• 2002

In this paper, a substrate network model to be used with BSIM3 MOSFET model for submicron MOSFETs in giga hertz frequencies and its direct parameter extraction with physically meaningful values are proposed. The proposed substrate network model includes a conventional resistance and single inductance originated from ring-type substrate contacts around active devices. Model parameters are extracted from S-parameter data measured from common-bulk configured MOS transistors with floating gate and use where needed without any optimization process. The proposed modeling technique has been applied to various-sized MOS transistors. The substrate model has been validated for frequency up to 300Hz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.1-9
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• 2006

We introduce our in-house program, NANOCAD, for the modeling and simulation of carrier transport in nanoscale MOSFET devices including quantum-mechanical effects, which implements two kinds of modeling approaches: the top-down approach based on the macroscopic quantum correction model and the bottom-up approach based on the microscopic non-equilibrium Green’s function formalism. We briefly review these two approaches and show their applications to the nanoscale bulk MOSFET device and silicon nanowire transistor, respectively.