• Journal of the Society of Naval Architects of Korea
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• v.56 no.4
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• pp.343-351
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• 2019

Green water impact may sometimes cause some structure damages on ship's bow deck. Prediction of proper design pressure against the green water impact is an essential task to prevent the possible damages on bow deck. This paper presents a computational method of the bow deck's design pressure against the green water impact. Large heave and pitch motions of ship are calculated by the time domain nonlinear strip method. Green water flow and pressure on bow deck are simulated by the predictor-corrector second kind upstream finite difference method. This green water simulation method is based on the shallow water wave equations expanded for moving bottom conditions. For various kind of ships such as container ship, VLCC, oil tanker and bulk carrier, the green water design pressures on bow deck are computed and discussed. Also, the obtained results of design pressure on bow deck are compared with those of the classification society rules and discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.

• Applied Chemistry for Engineering
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• v.9 no.6
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• pp.870-877
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• 1998

With impedance spectrum measurements, impedance was studied in the interface between sample solutions for $K^+-ion$ selective PVC membrane electrode containing neutral carriers [dibenzo-18-crown-6 (D18Cr6) and valinomycine (Val)]. Response characteristics of electrode were examined by measuring AC impedance spectra that were resulted from the chemical structure and the content of carrier, variation of plasticizer, membrane thickness, doping of base electrolytes, and concentration variation of sample solution. Transport characteristics of PVC membrane electrode were also studied. It was found that the equivalent circuit for the membrane in $K^+$ solution could be expressed by a series combination of solution resistance and a parallel circuit consisting of the bulk resistance and geometric capacitance of the membrane system. But the charge transfer resistance and Warburg resistance were overlapped a little in the low concentration and low frequency ranges. The carrier, D18Cr6 was best for electrode and impedance characteristics, and ideal electrode characteristics were appeared especially in case of doping of the base electrolyte[potassium tetraphenylborate(TPB)]. The optimum carrier content was about 3.23 wt% in case of D18Cr6 and Val. DBP was best as a plasticizer. As membrane thickness decreased the impedance characteristics was improved, but electrode characteristics were lowered for membrane thickness below the optimum. In the case of D18Cr6, the selectivity coefficients by the mixed solution method for the $K^+$ ion were the order of $NH_4{^+}>Ca^{2+}>Mg^{2+}>Na^+$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.308-309
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• 2012

One of the critical issues in the growth of multijunction solar cell is the formation of a highly doped Esaki interband tunnel diode which interconnects unit cells of different energy band gap. Small electrical and optical losses are the requirements of such tunnel diodes [1]. To satisfy these requirements, tens of nanometer thick gallium arsenide (GaAs) can be a proper candidate due to its high carrier concentration in low energy band gap. To obtain highly doped GaAs in molecular beam epitaxy, the temperatures of Si Knudsen cell (K-cell) for n-type GaAs and Be K-cell for p-type GaAs were controlled during GaAs epitaxial growth, and the growth rate is set to 1.75 A/s. As a result, the doping concentration of p-type and n-type GaAs increased up to $4.7{\times}10^{19}cm^{-3}$ and $6.2{\times}10^{18}cm^{-3}$, respectively. However, the obtained n-type doping concentration is not sufficient to form a properly operating tunnel diode which requires a doping concentration close to $1.0{\times}10^{19}cm^{-3}$ [2]. To enhance the n-type doping concentration, n-doped GaAs samples were grown with a lower growth rate ranging from 0.318 to 1.123 A/s at a Si K-cell temperature of $1,180^{\circ}C$. As shown in Fig. 1, the n-type doping concentration was increased to $7.7{\times}10^{18}cm^{-3}$ when the growth rate was decreased to 0.318 A/s. The p-type doping concentration also increased to $4.1{\times}10^{19}cm^{-3}$ with the decrease of growth rate to 0.318 A/s. Additionally, bulk resistance was also decreased in both the grown samples. However, a transmission line measurement performed on the n-type GaAs sample grown at the rate of 0.318 A/s showed an increased specific contact resistance of $6.62{\times}10^{-4}{\Omega}{\cdot}cm^{-2}$. This high value of contact resistance is not suitable for forming contacts and interfaces. The increased resistance is attributed to the excessively incorporated dopant during low growth rate. Further studies need to be carried out to evaluate the effect of excess dopants on the operation of tunnel diode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• Bulletin of the Korean Chemical Society
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• v.33 no.9
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• pp.3061-3070
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• 2012

Novel 2-hexylthieno[3,2-b]thiophene-containing conjugated molecules have been synthesized via a reduction reaction using tin chloride in an acidic medium. They exhibited good solubility in common organic solvents and good self-film and crystal-forming properties. The single-crystalline objects were fabricated by a solvent slow diffusion process and then were employed for fabricating field-effect transistors (FETs) along with thinfilm transistors (TFTs). TFTs made of 5 and 6 exhibited carrier mobility as high as 0.10-0.15 $cm^2V^{-1}s^{-1}$. The single-crystal-based FET made of 6 showed 0.70 $cm^2V^{-1}s^{-1}$ which was relatively higher than that of the 5-based FET (${\mu}=0.23cm^2V^{-1}s^{-1}$). In addition, we fabricated organic photovoltaic (OPV) cells with new 2-hexylthieno [3,2-b]thiophene-containing conjugated molecules and methanofullerene [6,6]-phenyl C61-butyric acid methyl ester ($PC_{61}BM$) without thermal annealing. The ternary system for a bulk heterojunction (BHJ) OPV cell was elaborated using $PC_{61}BM$ and two p-type conjugated molecules such as 5 and 7 for modulating the molecular energy levels. As a result, the OPV cell containing 5, 7, and $PC_{61}BM$ had improved results with an open-circuit voltage of 0.90 V, a short-circuit current density of 2.83 $mA/cm^2$, and a fill factor of 0.31, offering an overall power conversion efficiency (PCE) of 0.78%, which was larger than those of the devices made of only molecule 5 (${\eta}$~0.67%) or 7 (${\eta}$~0.46%) with $PC_{61}BM$ under identical weight compositions.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.171.2-171.2
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• 2016

The 2-dimensiona electron gas (2DEG) layers have opened tremendous interests in the heterooxide interfaces formed between two insulating materials, especially between LaAlO3 and $SrTiO_3$. The 2DEG layers exhibit extremely high mobility and carrier concentrations along with metallic transport phenomena unlike the constituent oxide materials, i.e., $LaAlO_3$ and $SrTiO_3$. The current work inserted artificially the interfacial layer, $Sr_xCa_{1-x}TiO_3$ between $LaAlO_3$ and $SrTiO_3$, with the aim to controlling the 2-dimensional transports. The insertion of the additional materials affect significantly their corresponding electrical transports. Such features have been probed using DC and AC-based characterizations. In particular, impedance spectroscopy was employed as an AC-based characterization tool. Frequency-dependent impedance spectroscopy have been widely applied to a number of electroceramic materials, such as varistors, MLCCs, solid electrolytes, etc. Impedance spectroscopy provides powerful information on the materials system: i) the simultaneous measurement of conductivity and dielectric constants, ii) systematic identification of electrical origins among bulk-, grain boundary-, and electrode-based responses, and iii) the numerical estimation on the uniformity of the electrical origins. Impedance spectroscopy was applied to the $LaAlO_3/Sr_xCa_{1-x}TiO_3/SrTiO_3$ system, in order to understand the 2-dimensional transports in terms of the interfacial design concepts. The 2-dimensional conduction behavior system is analyzed with special emphasis on the underlying mechanisms. Such approach is discussed towards rational optimization of the 2-dimensional nanoelectronic devices.

• Korean Journal of Materials Research
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• v.21 no.5
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• pp.243-249
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• 2011

To reduce manufacturing costs of crystalline silicon solar cells, silicon wafers have become thinner. In relation to this, the properties of the aluminium-back surface field (Al-BSF) are considered an important factor in solar cell performance. Generally, screen-printing and a rapid thermal process (RTP) are utilized together to form the Al-BSF. This study evaluates Al-BSF formation on a (111) textured back surface compared with a (100) flat back surface with variation of ramp up rates from 18 to $89^{\circ}C$/s for the RTP annealing conditions. To make different back surface morphologies, one side texturing using a silicon nitride film and double side texturing were carried out. After aluminium screen-printing, Al-BSF formed according to the RTP annealing conditions. A metal etching process in hydrochloric acid solution was carried out to assess the quality of Al-BSF. Saturation currents were calculated by using quasi-steady-state photoconductance. The surface morphologies observed by scanning electron microscopy and a non-contacting optical profiler. Also, sheet resistances and bulk carrier concentration were measured by a 4-point probe and hall measurement system. From the results, a faster ramp up during Al-BSF formation yielded better quality than a slower ramp up process due to temperature uniformity of silicon and the aluminium surface. Also, in the Al-BSF formation process, the (111) textured back surface is significantly affected by the ramp up rates compared with the (100) flat back surface.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.5
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• pp.93-102
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• 2020

The design of large complex mechanical systems, such as automobile, aircraft, and ship, is a kind of Multidisciplinary Design Optimization (MDO) because it requires both experience and expertise in many areas. With the rapid development of technology and the demand to improve human convenience, the complexity of these systems is increasing further. The design of such a complex system requires an integrated system design, i.e., MDO, which can fuse not only domain-specific knowledge but also knowledge, experience, and perspectives in various fields. In the past, the MDO relied heavily on the designer's intuition and experience, making it less efficient in terms of accuracy and time efficiency. Process integration and the design optimization framework mainly support MDO owing to the evolution of IT technology. This paper examined the procedure and methods to implement an efficient MDO with reasonable effort and time using RCE, an open-source PIDO framework. As a benchmarking example, the authors applied the proposed MDO methodology to a bulk carrier's conceptual design synthesis model. The validity of this proposed MDO methodology was determined by visual analysis of the Pareto optimal solutions.

• Journal of Navigation and Port Research
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• v.32 no.8
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• pp.577-582
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• 2008

In order to ascertain the effect of ship's speeds, in maneuver under the condition of strong cross current in the breakwater channel of Busan port, this paper is to deal with the analyses of vessel proximity measures, vessel controllability measures, and ship handlers' subjective evaluation measures of simulated maneuvers, which were carried out by 76 ship handlers who conned Panamax bulk carrier of 60,000 DWT, The set and drift of current are southwesterly and 2 knots. The speeds of the model ship are 5 knots & 10 knots respectively. The followings are concluded. ${(1)}$ In the approaches of the breakwater of Busan port, ship handlers psychologically tend not to give the drift angle of more than $10^{\circ}$ bemuse ship's head points out of the entrance. ${(2)}$ Ship handlers' subjective evaluation, vessel proximity and controllability measures are relatively larger under the speed of 5 knots than under that of 10 knots. due to direct pressure of strong current. ${(3)}$ A single index of controllability measures was suggested, by removing their units.