• Journal of Korean Society for Quality Management
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• v.21 no.2
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• pp.1-16
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• 1993

Early generations of products had little to no inherent capability to test themselves. The technologies involved often required only visual inspection and limited probing to troubleshoot the system once it was turned over to maintenance personnel. However, as the complexity of military and commercial systems grew, symptoms of failure became less noticeable to the operator. Therefore, the procedure to access, inspect, repair and replace a component became complicated, the requirements for personnel skill and testing equipment increased. and it took too long of a time to maintain a system. Meanwhile, the need for availability became more mission-critical and maintenance become very expensive. The obvious solution was to design in-system circuits or devices to self-test the primary system, the Built-In-Test(BIT) was born. This approach has continued right on up through present systems and is an integral part of systems now being designed. The object of this paper is to present a state-of-the-art research for filtering out the BIT diagnosis mistakes using Bayesian analysis and develop the algorithm for Redundant systems with BIT to improve BIT diagnosis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2123-2135
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• 1997

In this paepr, we consider resistive shorts on drain-source, drain-gate, and gate-source as well as opens in MOSFETs included in typical memory cell of VLSI SRAM. Behavior of memeory is observed by analyzing voltage at storage nodes of memeory and IDDQ(quiescent power supply current) through PSPICE simulation. Using this behavioral analysis, an effective testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ testing simultaeously is proposed. Built-In Self Test(BIST) circuit which detects faults in memories and Built-In Current Sensor(BICS) which monitors the power supply bus for abnormalities in quescent current are developed and imprlemented to improve the quality and efficiency of testing. Implemented BIST and BICS circuits can detect locations of faults and defects in order to repair faulty memories.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1E
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.73-79
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• 2009

With the advance of VLSI technology, the capacity and density of memories are rapidly growing. In this paper we proposed MRI (Memory built-in self Repair Imagination zone) as reallocation algorithm. All faulty cells of embedded memory are reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

• Journal of Applied Reliability
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• v.16 no.3
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• pp.224-230
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• 2016

Purpose: Military maintenance involves corrective and preventive actions carried out to keep a system in or restore it to a predetermined condition. This research develops an optimal maintenance cycle for aviation oil testing equipment with acceptable reliability level and minimum maintenance cost. Methods: The optimal maintenance policy in this research aims to satisfy the desired reliability level at the lowest cost. We assume that the failure process of equipment follows the power law non-homogeneous Poisson process model and the maintenance system is a minimal repair policy. Estimation and other statistical procedures (trend test and goodness of fit test) are given for this model. Results: With time varying failure rate, we developed reliability-based maintenance cost optimization model. This model will reduce the ownership cost through adopting a proactive reliability focused maintenance system. Conclusion: Based on the analysis, it is recommended to increase the current maintenance cycle by three times which is 0.5 year to 1.5 years. Because of the system's built-in self-checking features, it is not expected to have any problems of preventative maintenance cycle.

• The Journal of Information Technology
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• v.3 no.3
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• pp.57-65
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• 2000

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell of a 16M SDRAM installed in an Merged Memory with Logic(MML) generating the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by $0.25\mu\textrm{m}$ cell library. and verify the result of Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14N algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.114-121
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• 2013

As the weight of embedded memory within Systems-On-Chips(SoC) rapidly increases to 80-90% of the number of total transistors, the importance of testing embedded memory in SoC increases. This paper proposes IEEE std. 1500 wrapper based Programmable Memory Built-In Self-Test(PMBIST) architecture which can support various kinds of test algorithm. The proposed PMBIST guarantees high flexibility, programmability and fault coverage using not only March algorithms but also non-March algorithms such as Walking and Galloping. The PMBIST has an optimal hardware overhead by an optimum program instruction set and a smaller program memory. Furthermore, the proposed fault information processing scheme guarantees improvement of the memory yield by effectively supporting three types of the diagnostic methods for repair and diagnosis.