• 제목/요약/키워드: Buffers

검색결과 518건 처리시간 0.028초

메모리 자원 사용 효율성 증진을 위한 적응적 네트워크 이중 버퍼 모델 (An Adaptive Network Double Buffer Model for Efficient Memory Resource Usage)

  • 최창범;이승룡
    • 한국정보과학회논문지:시스템및이론
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    • 제33권11호
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    • pp.810-819
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    • 2006
  • 본 논문에서는 네트워크 통신에서 혼잡으로 인한 패킷의 손실을 최소화하기 위하여 새로운 버퍼 모델인 적응적인 이중 버퍼 모델을 제안한다. 이는 제약된 메모리 환경에서 송수신 버퍼가 서로의 여유 공간을 공유하여 패킷의 손실을 최대한 줄일 수 있는 버퍼 모델이다. 또한 리스트와 비슷한 성능을 지니는 본 버퍼 모델은 자유 리스트를 사용한 버퍼와 달리 메모리 누수로 인한 버블(bubbles) 현상을 방지하므로 제한된 환경의 네트워크 버퍼에 적용할 수 있으며 배열을 사용하는 경우와 비교 할 때 최대 100% 성능 향상을 기대할 수 있다.

EMI Prediction of Slew-Rate Controlled I/O Buffers by Full-Wave and Circuit Co-Simulation

  • Kim, Namkyoung;Hwang, Jisoo;Kim, SoYoung
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권4호
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    • pp.471-477
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    • 2014
  • In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

3-Line 버퍼를 사용한 실시간 Sobel 윤곽선 추출 블록 FPGA 구현 (FPGA Implementation for Real Time Sobel Edge Detector Block Using 3-Line Buffers)

  • 박찬수;김희석
    • 전기전자학회논문지
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    • 제19권1호
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    • pp.10-17
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    • 2015
  • 본 논문에서는 3-Line buffers를 사용하여 Sobel 윤곽선 추출 블록을 FPGA로 효율적으로 설계하여 구현하고자 한다. FPGA는 영상처리 알고리즘 중 하나인 Sobel 윤곽선 추출 알고리즘을 처리하기에 적절한 환경을 제공한다. 윤곽선 추출을 위한 방법으로는 파이프라인 방법을 사용하였다. Sobel 윤곽선 연산에서 윤곽선 강도 레벨을 결정하기 위하여 유한 상태 기계로 구현 된 마스크 연산을 이용한 모델을 제안한다. 효율적인 LUT 및 플리플롭의 사용으로 시스템의 성능이 향상됨을 입증하였다. 제안하는 3-line buffers을 이용한 Sobel 추출 연산은 Xilinx 14.2으로 합성하고 Virtex II xc2vp-30-7-FF896 FPGA device으로 구현하였다. Matlab을 이용하여 제안된 3-Line buffers 설계 시 PSNR 성능이 향상됨을 확인하였다.

유한 및 무한 용량 대기열을 가지는 선점 우선순위 M/G/1 대기행렬 (M/G/1 Preemptive Priority Queues With Finite and Infinite Buffers)

  • 김길환
    • 산업경영시스템학회지
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    • 제43권4호
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    • pp.1-14
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    • 2020
  • Recently, M/G/1 priority queues with a finite buffer for high-priority customers and an infinite buffer for low-priority customers have applied to the analysis of communication systems with two heterogeneous traffics : delay-sensitive traffic and loss-sensitive traffic. However, these studies are limited to M/G/1 priority queues with finite and infinite buffers under a work-conserving priority discipline such as the nonpreemptive or preemptive resume priority discipline. In many situations, if a service is preempted, then the preempted service should be completely repeated when the server is available for it. This study extends the previous studies to M/G/1 priority queues with finite and infinite buffers under the preemptive repeat-different and preemptive repeat-identical priority disciplines. We derive the loss probability of high-priority customers and the waiting time distributions of high- and low-priority customers. In order to do this, we utilize the delay cycle analysis of finite-buffer M/G/1/K queues, which has been recently developed for the analysis of M/G/1 priority queues with finite and infinite buffers, and combine it with the analysis of the service time structure of a low-priority customer for the preemptive-repeat and preemptive-identical priority disciplines. We also present numerical examples to explore the impact of the size of the finite buffer and the arrival rates and service distributions of both classes on the system performance for various preemptive priority disciplines.

3-노(盧)드 유한 버퍼 일렬대기행렬에서의 최적 버퍼 크기에 대한 분석 (Analysis of Optimal Buffer Capacities in 3-node Tandem Queues with Blocking)

  • 서동원
    • 한국경영과학회:학술대회논문집
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    • 한국경영과학회/대한산업공학회 2005년도 춘계공동학술대회 발표논문
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    • pp.881-889
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    • 2005
  • In this study, we consider characteristics of waiting times in single-server 3-node tandem queues with a Poisson arrival process, finite buffers and deterministic or non-overlapping service times at each queue. There are three buffers: one at the first node is infinite and the others are finite. The explicit expressions of waiting times in all areas of the systems, which are driven as functions of finite buffer capacities, show that the sojourn time does not depend on the finite buffer capacities and also allow one to compute and compare characteristics of waiting times at all areas of the system under two blocking policies: communication and manufacturing blocking. As an application of these results, moreover, an optimization problem which determines the smallest buffer capacities satisfying predetermined probabilistic constraints on waiting times is considered. Some numerical examples are also provided.

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THROUGHPUT ANALYSIS OF TWO-STAGE MANUFACTURING SYSTEMS WITH MERGE AND BLOCKING

  • Shin, Yang Woo;Moon, Dug Hee
    • Journal of applied mathematics & informatics
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    • 제33권1_2호
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    • pp.77-87
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    • 2015
  • Parallel lines are often used to increase production rate in many manufacturing systems where the main line splits into several lines in parallel, and after some operations, they merge into a main line again. Queueing networks with finite buffers have been widely used for modeling and analyzing manufacturing systems. This paper provides an approximation technique for multi-server two-stage networks with merge configuration and blocking which will be a building block for analysis of general manufacturing systems with parallel lines and merge configuration. The main idea of the method is to decompose the original system into subsystems that have two service stations with multiple servers, two buffers and external arrivals to the second stage are allowed. The subsystems are modeled by level dependent quasi-birth-and-death (LDQBD) process.

광통신용 HBT LD 구동 회로의 대역폭 개선을 위한 버퍼 구조에 관한 연구 (A Study on Buffer Structures to Improve the Bandwidth of HBT LD Driver for Optical Communication)

  • Hyeon Cheol Ki
    • 전자공학회논문지B
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    • 제32B권5호
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    • pp.710-719
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    • 1995
  • In LD driver with HBT's. the speed characteristics of HBT's are deteriorated very much mainly due to the source resistance(Rs) of the signal applied to the LD driving HBT. We improved the bandwidth of LD driver by 2-5GHz with modifications of EF buffer. Because the modified buffers are composed of EF structure, their bandwidths are decreased rapidly as Rs is increased. When Rs is large these buffers decrease the bandwidth of the LD driver rather than increase it. To solve this problem, we propose a new buffer structure which contaings new charging and discharging path for the parasitic collector capacitance of the HBT. For Rs>100${\Omega}$, it shows superior characteristics of improving bandwidth to the EF buffers. It also shows good gain characteristics.

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PLT buffer층의 삽입에 따른 강유전 PZT박막의 특성 향상 (Enhancement of the Ferroelectric Properties of Pb(La1Ti)O3 Thin Films with Pb(La1Ti)O3Buffers Fabricated by Pulsed Laser Deposition)

  • 임성훈;이은선;정현우;전경아;이상렬
    • 한국전기전자재료학회논문지
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    • 제18권2호
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    • pp.105-108
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    • 2005
  • The Pb(Zr,Ti)O$_3$ thin films were fabricated with Pb(La,Ti)O$_3$ buffers in-situ onto Pt/Ti/SiO$_2$/Si substrates by pulsed laser deposition method. We have observed the increase of the remanent polarization using PLT buffers. The remanent polarization value of 33.4 $\mu$C/$\textrm{cm}^2$ and the coercive field value of 66.4 kV/cm were obtained when the PLT tufter was deposited for 15 seconds. Enhancement of the polarization is resulted from the enhanced orientation of PZT thin film because of the PLT buffet layer.

Design of Two-Stage Class AB CMOS Buffers: A Systematic Approach

  • Martin, Antonio Lopez;Miguel, Jose Maria Algueta;Acosta, Lucia;Ramirez-Angulo, Jaime;Carvajal, Ramon Gonzalez
    • ETRI Journal
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    • 제33권3호
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    • pp.393-400
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    • 2011
  • A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 ${\mu}m$ CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 ${\mu}W$).

Packet Loss Patterns Adaptive Feedback Scheduling for Reliable Multicast

  • Baek, Jin-Suk;Kim, Cheon-Shik;Hong, You-Sik
    • Journal of Ubiquitous Convergence Technology
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    • 제1권1호
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    • pp.28-34
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    • 2007
  • Tree-based reliable multicast protocols provide scalability by distributing error-recovery tasks among several repair nodes. These repair nodes perform local error recovery for their receiver nodes using the data stored in their buffers. We propose a packet loss patterns adaptive feedback scheduling scheme to manage these buffers in an efficient manner. Under our scheme, receiver nodes send NAKs to repair nodes to request packet retransmissions only when the packet losses are independent events from other nodes. At dynamic and infrequent intervals, they also send ACKs to indicate which packets can be safely discarded from the repair node's buffer. Our scheme reduces delay in error recovery because the requested packets are almost always available in the repair node's buffers. It also reduces the repair node's workload because (a) each receiver node sends infrequent ACKs with non-fixed intervals and (b) their sending times are fairly distributed among all the receiver nodes.

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