• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.71-79
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• 2016

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.772-775
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• 2004

After Morris' Internet Worm in 1988, the stack buffer overflow hacking became generally known to hackers and it has been used to attack systems and servers very frequently. Recently, many researches tried to prevent it, and several solutions were developed such as Libsafe and StackGuard; however, these solutions have a few problems. In this paper we present a new stack buffer overflow attack prevention technique that uses the system call monitoring mechanism and memory address where the system call is made.

• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.258-262
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.784-789
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• 2007

This paper presents an implementation of a new type of architecture to improve an overflow problem on the network buffer. Each receiver channel of network system stores the message in its own buffer. If some receiver channel receives many messages, buffer overflow problem may occur for the channel. This paper proposes a network controller that implements a receiver channel with shared-memory to save all of the received messages from the every incomming channels. The proposed architecture is applied to ARINC-429, a real-time control network for commercial avionics system. For verifying performance of the architecture, ARINC-429 controller is designed using a SOPC platform, designed by Verilog and targeted to Xilinx Virtex-4 with a built-in PPC405 core.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.584-586
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• 2007

3D virtual modeling such as creation of a cyber city or landscape, or making a 3D GIS requires realistic textures. Automatic texture extraction using close range images is not yet efficient or easy in terms of data acquisition and processing. In this paper, common problems associated with automatic texture extraction from aerial photographs are explored. The ZI-buffer, which has depth and facet ID fields, is proposed to remove hidden pixels. The ZI-buffer algorithm reduces memory burden and identifies visible facets. The correct spatial resolution for facet gridding is tested. Error pixels in the visibility map were removed by filtering.

• Journal of the Korea Society for Simulation
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• v.12 no.2
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• pp.35-44
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• 2003

The effectiveness of buffer cache replacement algorithms is critical to the performance of I/O systems. In this paper, we propose the degree of inter-reference gap (DIG) based block replacement scheme that retains merits of the least recently used (LRU) such as simple implementation and good cache hit ratio (CHR) for general patterns of references, and improves CHR further. In the proposed scheme, cache blocks with low DIGs are distinguished from blocks with high DIGs and the replacement block is selected among high DIGs blocks as done in the low inter-reference recency set (LIRS) scheme. Thus, by having the effect of the partitioning the cache memory dynamically based on DIGs, CHR is improved. Trace-driven simulation is employed to verified the superiority of the DIG based scheme and shows that the performance improves up to about 175% compared to the LRU scheme and 3% compared to the LIRS scheme for the same traces.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.4
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• pp.115-120
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• 2011

Recently flash memory is widely used in various mobile devices as storage medium. Nonvolatile memory can be divided into two categories: NAND- and NOR-type flash memory. NOR flash memory is mainly used to store instruction codes for operation; while NAND for data storage. However, NAND does show more economical benefits, that is, it is approximately 30~40% cheaper than NOR flash. Therefore it can be useful to improve NAND flash performance by replacing NOR flash with NAND flash combining with various buffer systems.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.123-126
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• 2000

In this paper, we are proposed to pushing window input buffer A.T.M Switch that is not use memory read and write of general window police. Pushing window switch is superior to general window switch in performance but is large to general window switch in cross point number. Max throughput and Cell occupying probability results are verified by analysis an simulation. The evaluation of performance is max throughput and cell loss probability and mean queue length.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.446-448
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• 2006

DRAM with ECC is used widely and the size of DRAW increases. According to this, DRAM initial time, especially the time to make the whole area typical value, 0, increases. This paper introduces the method that without any additional hardware, using characteristic of DRAM and DRAM controller, minimize that memory initial time. Conservative reordering - it eliminates DRAM read time and makes write buffer used - reduces initial time to make the whole DRAM area 0, by 95.36% for DDR DRAM. 9341% for Rambus DRAM.