• 한국전기전자재료학회논문지
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• 제37권3호
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• pp.332-336
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• 2024

High-energy bandgap material silicon carbide (SiC) is gaining attention as a next-generation power semiconductor material, and in particular, SiC-based MOSFETs are developed as representative power semiconductors to increase the breakdown voltage (BV) of conventional planar structures. However, as the size of SJ (Super Junction) MOSFET devices decreases and the depth of pillars increases, it becomes challenging to uniformly form the doping concentration of pillars. Therefore, a structure with different doping concentrations segmented within the pillar is being researched. Using Silvaco TCAD simulation, a SJ VVD (vertical variation doping profile) MOSFET with three different doping concentrations in the pillar was studied. Simulations were conducted for the width of the pillar and the doping concentration of N-epi, revealing that as the width of the pillar increases, the depletion region widens, leading to an increase in on-specific resistance (R_on,sp) and breakdown voltage (BV). Additionally, as the doping concentration of N-epi increases, the number of carriers increases, and the depletion region narrows, resulting in a decrease in R_on,sp and BV. The optimized SJ VVD MOSFET exhibits a very high figure of merit (BFOM) of 13,400 KW/cm², indicating excellent performance characteristics and suggesting its potential as a next-generation highperformance power device suitable for practical applications.

• 한국전기전자재료학회논문지
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• 제17권8호
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• pp.823-829
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• 2004

In this paper, non-self-aligned SiGe HBTs with ${f}_\tau$ and${f}_max $above 50 GHz have been fabricated using an RPCVD(Reduced Pressure Chemical Vapor Deposition) system for wireless applications. In the proposed structure, in-situ boron doped selective epitaxial growth(BDSEG) and TiSi$_2$ were used for the base electrode to reduce base resistance and in-situ phosphorus doped polysilicon was used for the emitter electrode to reduce emitter resistance. SiGe base profiles and collector design methodology to increase ${f}_\tau$ and${f}_max $ are discussed in detail. Two SiGe HBTs with the collector-emitter breakdown voltages ${BV}_CEO$ of 3 V and 6 V were fabricated using SIC(selective ion-implanted collector) implantation. Fabricated SiGe HBTs have a current gain of 265 ∼ 285 and Early voltage of 102 ∼ 120 V, respectively. For the $1\times{8}_\mu{m}^2$ emitter, a SiGe HBT with ${BV}_CEO$= 6 V shows a cut-off frequency, ${f}_\tau$of 24.3 GHz and a maximum oscillation frequency, ${f}_max $of 47.6 GHz at $I_c$of 3.7 mA and$V_CE$ of 4 V. A SiGe HBT with ${BV}_CEO$ = 3 V shows ${f}_\tau$of 50.8 GHz and ${f}_max $ of 52.2 GHz at $I_c$ of 14.7 mA and $V_CE$ of 2 V.

• Journal of Electrical Engineering and information Science
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• 제2권4호
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• pp.106-110
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• 1997

A new SOI NMOSFET with a 'LOCOS-like' shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication was tried. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3${\mu}{\textrm}{m}$ SOI devices with V\ulcorner of 0.77V and Tox=7.6nm is 360$mutextrm{A}$/${\mu}{\textrm}{m}$ at V\ulcorner\ulcorner=3.5V and V\ulcorner=2.5V. Improved breakdown characteristics were obtained and the BV\ulcorner\ulcorner\ulcorner(the drain voltage for 1 nA/${\mu}{\textrm}{m}$ of I\ulcorner at V=\ulcorner\ulcorner=0V) of the device with L\ulcorner\ulcorner=0.3${\mu}{\textrm}{m}$ under the floating body condition was as high as 3.7 V. Problems for the new scheme are also addressed and more advanced device structure based on the proposed scheme is proposed to solve the problems.

• 전기전자학회논문지
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• 제11권4호
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• pp.158-164
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• 2007

본 논문에서는 전력용 스위칭 소자로 널리 활용되고 있는 IGBT 소자 중 수평 게이트 구조보다 우수한 특성을 지닌 트렌치 게이트 IGBT(TIGBT) 구조를 채택하여, 기존의 TIGBT가 갖는 구조적 한계를 극복하고 좀 더 우수한 전기적 특성을 갖는 새로운 구조의 수직형 TIGBT를 제안하였다. 첫 번째로 제안한 IGBT 소자는 P+컬렉터를 산화막으로 고립시킴으로서 N-드리프트 층으로의 정공 주입효율을 극대화하여 기존 구조보다 더 낮은 순방향 전압강하를 얻도록 설계된 구조이다. 두 번째 제안한 구조는 양 게이트 사이의 P-베이스 구조를 볼록하게 형성함으로서 게이트 쪽으로 집중되는 전계의 일부를 접합부 쪽으로 유도하여 기존 구조보다 더 높은 항복전압을 얻을 수 있다. 또한 P-베이스의 볼록한 구조가 턴-오프 시 정공의 흐름을 개선시켜 기존 구조보다 더 빠른 턴-오프 시간을 갖게 된다. 시뮬레이션 결과 첫 번째 구조의 특징은 2.4V의 순방향 전압강하 특성을 갖는 기존의 IGBT 구조보다 상당히 낮은 2.1V의 순방향 전압강하 특성을 나타냈으며, 두 번째 구조는 기존의 IGBT 보다 10V정도 높아진 항복전압 특성을 보였다. 또한 두 번째 구조에서 기존 구조와 비교해볼 때 9ns 정도 빠른 턴-오프 시간을 보였다. 최종적으로 제안된 새로운 구조의 TIGBT는 위 두 구조가 갖는 우수한 전기적 특성을 모두 갖도록 결합한 것이며, 시뮬레이션 결과 기본의 TIGBT 소자보다 순방향 전압강하, 항복특성, 그리고 턴 오프 특성이 모두 우수한 결과를 나타냈다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.207-209
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• 2004

Currently, for satisfying the needs of scaled MOSFET's a high quality thin oxide dielectric is desired because the properties of conventional $SiO_2$ film are not acceptable for these very small sized transistors. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over conventional $SiO_2$, to obtain the superior characteristics of ultra thin dielectric films, $N_2O$ grown thin oxynitride has been proposed as a dielectric growtuanneal ambient. In this study the authors observed process characteristics of $N_2O$ grown thin dielectric. In view points of the process characteristics of MOS capacitor, the sheet resistance of 4.07$[\Omega/sq.]$, the film stress of $1.009e^{10}[dyne/cm^2]$, the threshold voltage$(V_t)$ of 0.39[V], the breakdown voltage(BV[V]) of 11.45[V] was measured in PMOS. I could achieve improved electrical characteristics and reliability for deep submicron MOSFET devices with $N_2O$ thin oxide.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.284-288
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• 2013

Power MOSFETs(Metal Oxide Semiconductor Field Effect Transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. We have experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical MOSFET. The device is fabricated as $8.25{\mu}m$ cell pitch and $4.25{\mu}m$ gate width. The performances of device with various p base doping concentration are compared at Vth from 1.77 V to 4.13 V. Also the effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for various applications can be further optimized at power device.

• 전자공학회논문지A
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• 제30A권10호
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• pp.59-66
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• 1993

PZT thin film deposited by rf magnetron sputtering was annealed by rapid thermal process(RTP) in PbO ambient to prevent vaporing of Pb and interface reactions. Si and TiN/Ti/Si substrates were prepared to survey application of TiN/Ti layer which can prevent interface interaction with Si and crack of PZT thin films. As temperature increased. PZT thin films surface on Si substrate appeared more severe cracks which should affect electrical properties deadly. TiN/Ti(40-150${\mu}{\Omega}{\cdot}cm$) layer applied for buffer layer suppressed interface interaction and film cracking. The measured leakage current(LC) and breakdown voltage(BV) of PZT thin film on TiN/Ti/Si substrate annealed at 650$^{\circ}$C for 15 sec (thickness of 2500$\AA$) were 38 nA/cm2 and 3.5 MV/cm and dielectric constant was 310 at 1 MHz, and remanent polarization (Pr) and coercive field (Ec) were 6.4${\mu}C/cm^{2}$ and 0.2MV/cm at 60 Hz, respectively.

• 전자공학회논문지A
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• 제32A권2호
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• pp.66-72
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• 1995

Using the Si/SiGe layer grown by solid source molecular beam epitaxy(SSMBE) on the LOCOS-patterned wafers, an emitter-base self-aligned hterojunction biplar transistor(HBT) with the polysilicon-emitter and the silicon germanium(SiGe) base has been fabricated. Trech isolation process, planarization process using a chemical-mechanical poliching, and the selectively implanted collector(SIC) process were performed. A titanium disilicide (TiSi$_{2}$), as a base electrode, was used to reduce an extrinsic base resistance. To prevent the strain relaxation of the SiGe epitaxial layer, low temperature (820${^\circ}C$) annealing process was applied for the emitter-base junction formation and the dopant activation in the arsenic-implanted polysilicon. For the self-aligned Si/SiGe HBT of 0.9${\times}3.8{\mu}m^{2}$ emitter size, a cut-off requency (f$_{T}$) of 17GHz, a maximum oscillation frequency (f$_{max}$) of 10GHz, a current gian (h$_{FE}$) of 140, and an emitter-collector breakdown voltage (BV$_{CEO}$) of 3.2V have been typically achieved.

• 전자공학회논문지A
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• 제30A권12호
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• pp.51-59
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• 1993

A 4${\times}10^{19}cm^{3}$ carbon-doped base AlGaAs/GaAs HBY was grown using carbontetracholoride(CCl$_4$) by atmospheric pressure MOCVD. Abruptness of emitter-base junction was characterized by SIMS(secondary ion mass spectorscopy) and the doping concentration of base layer was confirmed by DXRD(double crystal X-ray diffractometry). Mesa-type HBTs were fabricated using wet etching and lift-off technique. The base sheet resistance of R$_{sheet}$=550${\Omega}$/square was measured using TLM(transmission line model) method. The fabricated transistor achieved a collector-base junction breakdown voltage of BV$_{CBO}$=25V and a critical collector current density of J$_{O}$=40kA/cm$^2$ at V$_{CE}$=2V. The 50$\times$100$\mu$$^2$ emitter transistor showed a common emitter DC current gain of h$_{FE}$=30 at a collector current density of JS1CT=5kA/cm$^2$ and a base current ideality factor of ηS1EBT=1.4. The high frequency characterization of 5$\times$50$\mu$m$^2$ emitter transistor was carried out by on-wafer S-parameter measurement at 0.1~18.1GHz. Current gain cutoff frequency of f$_{T}$=27GHz and maximum oscillation frequency of f$_{max}$=16GHz were obtained from the measured Sparameter and device parameters of small-signal lumped-element equivalent network were extracted using Libra software. The fabricated HBT was proved to be useful to high speed and power spplications.