• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.14 no.4
• /
• pp.2037-2042
• /
• 2013

A TCO-less palladium (Pd) catalytic layer on the glass substrate was assessed as the counter electrode (CE) in a dye sensitized solar cell (DSSC) to confirm the stability of Pd with the $I^-/I_3{^-}$electrolyte on the DSSC performance. A 90nm-thick Pd film was deposited by a thermal evaporator. Finally, DSSC devices of $0.45cm^2$ with glass/FTO/blocking layer/$TiO_2$/dye/electrolyte(10 mM LiI + 1 mM $I_2$ + 0.1 M $LiClO_4$ in acetonitrile solution)/Pd/glass structure was prepared. We investigated the microstructure and photovoltaic property at 1 and 12 hours after the sample preparation. The optical microscopy, field emission scanning electron microscopy (FESEM), cyclic voltammetry measurement (C-V), and current voltage (I-V) were employed to measure the microstructure and photovoltaic property evolution. Microstructure analysis showed that the corrosion by reaction between the Pd layer and the electrolyte occurred as time went by, which led the decrease of the catalytic activity and the efficiency. I-V result revealed that the energy conversion efficiency after 1 and 12 hours was 0.34% and 0.15%, respectively. Our results implied that we might employ the other non-$I^-/I_3{^-}$electrolyte or the other catalytic metal layers to guarantee the long term stability of the DSSC devices.

• Membrane Journal
• /
• v.33 no.4
• /
• pp.191-200
• /
• 2023

Polyethersulfone (PES) is a widely employed membrane material for water and industrial purification applications owing to its hydrophilicity and ease of phase separation. However, PES membranes and filters prepared using the nonsolvent induced phase separation method often encounter significant flux decline due to pore clogging and cake layer formation on the dense membrane surfaces. Our investigation revealed that tight microfiltration or loose ultrafiltration membranes can be subject to physical fouling due to the formation of a dense skin layer on the bottom side caused by water intrusion to the gap between the shrank membrane and the substrate. To investigate the effect of the bottom surface porosity on membrane fouling, two membranes with the same selective layers but different sub-layer structures were prepared using single and double layer casting methods, respectively. The double layered PES membrane with highly porous bottom surface showed high flux and physical fouling tolerance compared to the pristine single layer membrane. This study highlights the importance of physical optimization of the membrane structure to prevent membrane fouling.

• Journal of the Microelectronics and Packaging Society
• /
• v.29 no.4
• /
• pp.29-34
• /
• 2022

A fabrication process of smart windows with controllable visible light transmittance by using retardation films is proposed. The 𝛌/4-phase retardation films that can convert a linearly polarized light into circularly polarized light are achieved through photo-alignment layers and reactive mesogen (RM) coating process. Two sheets of the fabricated retardation films with different orientation angles induced to light transmission mode (45°/-45°) and light blocking mode (45°/45°) for visible wavelength. We evaluated retardation characteristics according to the thickness of the birefringent RM material and found out the optimal condition for the film with 𝚫n·d of 𝛌/4-phase. The proposed structure of the smart window exhibited the light blocking ratio improved by more than 20% in the visible wavelength (380 nm to 780 nm). Finally, it was confirmed that the feasibility of the window structure by applying to a prototype for a smart window with a size of 150 × 150 mm².

• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.4
• /
• pp.49-53
• /
• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• ETRI Journal
• /
• v.35 no.3
• /
• pp.425-430
• /
• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.2
• /
• pp.167-173
• /
• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• Smart Structures and Systems
• /
• v.16 no.5
• /
• pp.759-780
• /
• 2015

Based on the theory of piezoelasticity, the static performance of a piezoelectric bilayer cantilever fully covered with electrodes on the upper and lower surfaces is studied. Three models are considered, i.e., the sensor model, the driving displacement model and the blocking force model. By establishing suitable boundary conditions and proposing an appropriate Airy stress function, the exact solutions for piezoelectric bilayer cantilevers are obtained, and the effect of ambient thermal excitation is taken into account. Since the layer thicknesses and material parameters are distinguished in different layers, this paper gives unified solutions for composite piezoelectric bilayer cantilevers including piezoelectric bimorph and piezoelectric heterogeneous bimorph, etc. For some special cases, the simplifications of the present results are compared with other solutions given by other researches based on one-dimensional constitutive equations, and some amendments have been found. The present investigation shows: (1) for a PZT-4 piezoelectric bimorph, the amendments of tip deflections induced by an end shear force, an end moment or an external voltage are about 19.59%, 23.72% and 7.21%, respectively; (2) for a PZT-4-Al piezoelectric heterogeneous bimorph with constant layer thicknesses, the amendments of tip deflections induced by an end shear force, an end moment or an external voltage are 9.85%, 11.78% and 4.07%, respectively, and the amendments of the electrode charges induced by an end shear force or an end moment are both 1.04%; (3) for a PZT-4-Al piezoelectric heterogeneous bimorph with different layer thicknesses, the maximum amendment of tip deflection approaches 23.72%, and the maximum amendment of electrode charge approaches 31.09%. The present solutions can be used to optimize bilayer devices, and the Airy stress function can be used to study other piezoelectric cantilevers including multi-layered piezoelectric cantilevers under corresponding loads.

• Korean Journal of Optics and Photonics
• /
• v.8 no.4
• /
• pp.327-332
• /
• 1997

We fabricated the high speed 1.55${\mu}{\textrm}{m}$ distributed feedback laser diodes (DFB-LD) using both two-step mesa etching process and semi-insulating InP current blocking layers. The devices characteristics were threshold current of ~15mA, slope efficiency of ~0.13mW/mA, and dynamic resistance of ~6.0Ω, with as-cleaved facets. The fabricated DFB-LD showed the single longitudinal mode with more than 40dB up to 6 $I_{th}$(CW condition), emitting at the wavelength of 0.546${\mu}{\textrm}{m}$. The -3dB bandwidth was >10㎓ at the driving current of 27mA, and the maximum -3dB bandwidth was ~18㎓ at 90 mA current, showing the superior frequency response of SI-PBH DFB-LD. In the 10Gb/s transmission experiment for 1.55${\mu}{\textrm}{m}$ DFB-LD module, maximum 10 km of single mode fiber(SMF) or 80 km of dispersion shifted fiber (DSF) could be transmitted with error free.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.1092-1095
• /
• 2001

Steady state thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin with a thickness of 25${\mu}$m. It was assumed that the generated heat which is mainly by the on-state voltage drop, 9V for 12kV diode, is dissipated by way of the conduction through diodes layers to bonding wire and of the convection at the surface of passivating resin. It was predicted by the thermal analysis that the temperature rise of a pn junction of the 12kV diode can reach at the range of 16∼34$^{\circ}C$ under the given boundary conditions. The thickness and thermal conductivity(0.3∼3W/m-K) of the passivating resin did little effect to lower thermal resistance of the diode. As the length of the bonding wire increased, which means the distance of heat conduction path became longer, the thermal resistance increased considerably. The thermal analysis results imply that the generated heat of the diode is dissipated mainly by the conduction through the route of diode-dummy wafer-bonding wire, which suggests to minimize the length of the wire for the lowest thermal resistance.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.6
• /
• pp.17-23
• /
• 2000

In this study, we prepared red organic light-emitting-diode(OLED) with a fluorescent dye(Sq)-doped and inserted between emission and cathode layer 1,3-bis(5-p-t-butylphenyl)-1,3,4-oxadiazol-2-yl)benzene (OXD7) or/and tris(8-hydroxyquinoline) aluminum ($Alq_3$) layers for increasing electroluminescent(EL) efficiency. This inserting effect has been observed and EL mechanism characteristics have been examined. The hole transfer layer is a N,N'-diphenyl-N,N'-bis-(3-methyl phenyl)-1,1'-diphenyl-4,4'-diamine (TPD), and the host and guest materials of emission layer is $Alq_3$ and bis[1-methyl-3,3'-dimethyl-2-indorindiylmethyl] squaraine (Sq), respectively. For the inserting of $Alq_3$, emission efficiency increased. But we can not obtained highly pure red emission owing to the emission of inserting $Alq_3$ layer. The inserting of OXD7 makes hole block and accumulate. Because of increasing recombination probability of electron and hole, highly pure red color can be held. Simultaneously brightness characteristics and emission efficiency could improve.