• Journal of Korea Multimedia Society
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• v.11 no.8
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• pp.1093-1100
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• 2008

Feistel and SPN are the two main structures in designing a block cipher algorithm. Unlike Feistel, an SPN has an asymmetric structure in encryption and decryption. In this paper we propose an SPN algorithm which has a symmetric structure in encryption and decryption. The whole operations in our SPN algorithm are composed of the even numbers of N rounds where the first half of them, 1 to N/2, applies function and the last half of them, (N+1)/2 to N, employs inverse function. Symmetry layer is executed to create a symmetry block in between function layer and inverse function layer. AES encryption and decryption algorithm, whose safety is already proved, are exploited for function and inverse function, respectively. In order to be secure enough against the byte or word unit-based attacks, 32bit rotation and simple logical operations are performed in symmetry layer. Due to the simplicity of the proposed encryption and decryption algorithm in hardware configuration, the proposed algorithm is believed to construct a safe and efficient cipher in Smart Card and RFID environments where electronic chips are built in.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.55-61
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• 2003

The Data Encryption Standard(DES) has been a worldwide standard for over 20 years. DES is one of the block encryption techniques which ciphers 64-bit input data blocks using a 56-bit private key. The DES algorithm transforms 64-bit input in a series of steps into a 64-bit output. Thus, it is impossible to deduce the plaintext from the ciphertext which encrypted by this algorithm without the key. This paper presents an implementation of RFID roader system using the DES algorithm. An implemented system enhances the credibility of the encryption algorithm by using the Cipher Block Chining(CBC). Experimental results also show that the implemented system has better performance over the conventional commercial product.

• The Journal of Society for e-Business Studies
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• v.20 no.1
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• pp.89-97
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• 2015

In the various application environments on the internet, we use verified cipher algorithm to protect personal information of electronic commerce or application environments. Even so, if an application method isn't proper, the information you want to keep can be intercepted. This thesis studied about result of Padding Oracle Attack, an application environment which apply CBC|CBC operational mode based on block cipher and BOZ padding method.

• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.201-204
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• 2005

Twofish is a 128-bit block cipher that accepts a variable-length key up to 256 bits. The cipher is a 16­round Feistel network with a bijective F function made up of four key-dependent 8-by-8-bit S-boxes, a fixed 4­by-4 maximum distance separable matrix over Galois Field$(GF (2^8)$, a pseudo-Hadamard transform, bitwise rotations, and a carefully designed key schedule. In this paper, the Twofish is modeled in VHDL and simulated. Hardware implementation gives much better performance than software-based approaches.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.11
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• pp.5717-5730
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• 2019

LBlock-s is the core block cipher of authentication encryption algorithm LAC, which uses the same structure of LBlock and an improved key schedule algorithm with better diffusion property. Using the differential properties of the key schedule algorithm and the cryptanalytic technique which combines impossible boomerang attacks with related-key attacks, a 15-round related-key impossible boomerang distinguisher is constructed for the first time. Based on the distinguisher, an attack on 22-round LBlock-s is proposed by adding 4 rounds on the top and 3 rounds at the bottom. The time complexity is about only 2^68.76 22-round encryptions and the data complexity is about 2⁵⁸ chosen plaintexts. Compared with published cryptanalysis results on LBlock-s, there has been a sharp decrease in time complexity and an ideal data complexity.

• Journal of the Korea Society of Computer and Information
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• v.16 no.1
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• pp.143-151
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• 2011

Plaintext and key are independent in the existing block cipher. Also, encryption/decryption is performed by using structural features. Therefore, the external environment of suggested mixed cryptographic algorithm is identical with the existing ones, but internally, features of the existing block cipher were meant to be removed by making plaintext and key into dependent functions. Also, to decrease the loads on the authentication process, authentication add-on with dependent characteristic was included to increase the use of symmetric cryptographic algorithm. Through the simulation where the proposed cryptosystem was implemented in the chip level, we show that our system using the shorter key length than the length of the plaintext is two times faster than the existing systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.404-406
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• 2015

This paper describes a small-area hardware implementation of the block cipher algorithm CLEFIA-128 which supports for 128-bit master key. A compact structure using single data processing block is adopted, which shares hardware resources for round transformation and the generation of intermediate values for round key scheduling. In addition, data processing and key scheduling blocks are simplified by utilizing a modified GFN(generalized Feistel network) and key scheduling scheme. The CLEFIA-128 crypto-processor is verified by FPGA implementation. It consumes 823 slices of Virtex5 XC5VSX50T device and the estimated throughput is about 105 Mbps with 145 MHz clock frequency.

• KIPS Transactions on Computer and Communication Systems
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• v.10 no.4
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• pp.101-106
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• 2021

Quantum algorithms and quantum computers can break the security of many of the ciphers we currently use. If Grover's algorithm is applied to a symmetric key cipher with n-bit security level, the security level can be lowered to (n/2)-bit. In order to apply Grover's algorithm, it is most important to optimize the target cipher as a quantum circuit because the symmetric key cipher must be implemented as a quantum circuit in the oracle function. Accordingly, researches on implementing AES(Advanced Encryption Standard) or lightweight block ciphers as quantum circuits have been actively conducted in recent years. In this paper, korean lightweight block cipher LEA was optimized and implemented as a quantum circuit. Compared to the previous LEA quantum circuit implementation, quantum gates were used more, but qubits were drastically reduced, and performance evaluation was performed for this tradeoff problem. Finally, we evaluated quantum resources for applying Grover's algorithm to the proposed LEA implementation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.307-311
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• 2004

This paper presents an efficient architecture that optimizes the design of SEED S-box using composite field arithmetic. SEED is the Korean standard 128-bit block cipher algorithm developed by Korea Information Security Agency. The nonlinear function S-box is the most costly operation in terms. of size and power consumption, taking up more than 30% of the entire SEED circuit. Therefore the S-box design can become a crucial factor when implemented in systems where resources are limited such as smart cards. In this paper, we transform elements in $GF(2^8)$ to composite field $GF(((2^2)^2)^2)$ where more efficient computations can be implemented and transform the computed result back to $GF(2^8)$. This technique reduces the S-box portion to 15% and the entire SEED algorithm can be implemented at 8,700 gates using Samsung smart card CMOS technology.