• 한국정보통신설비학회:학술대회논문집
• /
• 2005.08a
• /
• pp.427-430
• /
• 2005

A multi-code biorthogonal code keying (MBCK) system consists of multiple waveform coding blocks, and the sum of output codewords is transmitted. Drawback of MBCK is that it requires amplifier with high linearity because its output symbol is multi-level. MBCK with constant amplitude precoding block (CA-MBCK) has been proposed, which guarantees sum of orthogonal codes to have constant amplitude. The precoding block in CA-MBCK is a redundant waveform coder whose input bits are generated by processing the information bits. Redundant bits of constant amplitude coded CA-MBCK are not only used to make constant amplitude signal but also used to improve the BER performance at the receiver. In this paper, we proposed a transmission scheme which combines CA-MBCK with $Q^2PSK$ modulation to improve bandwidth efficiency of CA-MBCK and also uses chip interleaving to maintain a constant amplitude feature of CA-MBCK. bandwidth efficiency of a proposed transmission scheme is increased fourfold. And the BER performance of the scheme is same as that of CA-MBCK.

• The KIPS Transactions:PartC
• /
• v.10C no.2
• /
• pp.233-240
• /
• 2003

In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interaction numbers, interleaver block sizes and code rates.

• The KIPS Transactions:PartA
• /
• v.18A no.4
• /
• pp.135-142
• /
• 2011

This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

• Journal of IKEEE
• /
• v.19 no.2
• /
• pp.168-175
• /
• 2015

In this paper, we propose FPGA design technique for rotating LED display device which is capable of displaying videos with the use of the afterimage effect. The proposed technique is made up of image data correction process based on inverse gamma correction and error diffusion, block interleaving process, and data serial output process. The data correction process based on inverse gamma correction and error diffusion is an image data correction step in which image data received are corrected by inverse gamma correction process to convert the data into linear brightness characteristics, and by error diffusion process to reduce the brightness reduction phenomenon in low-gray-level which is caused by inverse gamma correction. In the block interleaving process, the data of the frames entered transversely are first saved in accordance with entrance order, and then only the longitudinal image data are read. The data serial output process is applied to convert the parallel data in a rotating location into serial data and send them to LED Driver IC, in order to send data which will be displayed on high-speedy rotating LED Bar. To evaluate the accuracy of the proposed FPGA design technique, this paper used XC6SLX45-FG484, a Spartan 6 family of Xilinx, as FPGA, and ISE 14.5 as a design tool. According to the evaluation analysis, it was found that goal values were consistent with simulation values in terms of accurate operation of inverse gamma and error diffusion correction, block interleaving operation, and serialized operation of image data.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.132-135
• /
• 2000

In this paper, we propose to exploit a multi-code CDMA scheme for power line communication (PLC) systems, and its performance on non-Gaussian impulse and harmonic noises is presented. The proposed multi-code CDMA scheme utilizes convolutional coding and block interleaving to combat with the non-Gaussian noises, and simulation results indicate effective alleviation of these noises, and thus significant bit error rate improvement by the proposed scheme even under strict restriction of frequency band allowed in PLC systems.

• Proceedings of the IEEK Conference
• /
• 2003.11c
• /
• pp.200-203
• /
• 2003

By minimizing the burst error of data and correcting the error, we can define the convolution coding and interleaving in IEEE 802.11a wireless tan system. Two step block interleaver was decided by coded bits per OFDM symbol and due to this it comes to the delay time in IEEE 802.11a. This is the point of the question which we must consider. We try to decrease the delay time by all 48-clock from interleavings, and we have proposed a way carried out the interleaving outputs per symbol. So in comparison with the existing interleaver, we can decrease the delay time in reading and writing data, as well as reduce the delay time of bit re-ordering per symbol. Also this scheme is apply in all x-QAM cases.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.48 no.4
• /
• pp.15-23
• /
• 2011

An interleaver rearranges a channel-encoded data in the symbol unit to spread burst errors occurred in channels into random errors. Thus, the interleaving process makes it difficult for a receiver, who does not have information of the interleaver parameters used in the transmitter, to de-interleave an unknown interleaved signal. Recently, various researches on the reconstruction of an unknown interleaved signal have been studied in many places of literature by estimating the interleaver parameters. They, however, have been mainly focused on the estimation of the block interleaver parameters required to reconstruct the de-interleaver. In this paper, as an extension of the previous researches, we estimate the convolutional interleaver parameters, e.g., the number of shift registers, a shift register depth, and a codeword length, required to de-interleave the unknown data stream, and propose the de-interleaving procedure by reconstructing the de-interleaver.

• The KIPS Transactions:PartB
• /
• v.10B no.2
• /
• pp.143-150
• /
• 2003

Error concealment plays an important role in combating transmission errors. Methods of error concealment which produce better quality are generally of higher complexity, thus making some of the more sophisticated algorithms is not suitable for real-time applications. In this paper, we develop temporal and spatial error resilient video encoding and data hiding approach to facilitate the error concealment at the decoder. Block interleaving scheme is introduced to isolate erroneous blocks caused by packet losses for spatial area of error resilience. For temporal area of error resilience, data hiding is applied to the transmission of parity bits to protect motion vectors. To do error concealment quickly, a set of edge features extracted from a block is embedded imperceptibly using data hiding into the host media and transmitted to decoder. If some part of the media data is damaged during transmission, the embedded features are used for concealment of lost data at decoder. This method decreases a complexity of error concealment by reducing the estimation process of lost data from neighbor blocks. The proposed data hiding method of parity bits and block features is not influence much to the complexity of standard encoder. Experimental results show that proposed method conceals properly and effectively burst errors occurred on transmission channel like Internet.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.8
• /
• pp.63-72
• /
• 2012

In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.

• Journal of IKEEE
• /
• v.2 no.2 s.3
• /
• pp.285-293
• /
• 1998

This paper presents unequal error protection and error concealment techniques far robust H.263 video transmission over mobile channels. The proposed error protection scheme has three major features. First, it has the capability of preventing the loss of synchronization information in H.263 video stream as much as possible that the H.263 decoder can resynchronize at the next decoding point, if errors are occurred. Secondly, it employs an unequal error protection scheme to support variable coding rates using rate compatible punctured convolutional (RCPC) codes, dividing the encoded stream into two classes. Finally, a macroblock-interleaving scheme is employed in order to minimize the corruption of consecutive macroblocks due to burst errors, which can make a proper condition for error concealment. In addition, to minimize the spatial error propagations due to the variable length codes, a fast resynchronization scheme at the group of block layer is developed for recovering subsequent error-free macroblocks following the damaged macroblock. futhermore, error concealment techniques based on both side match criterion and overlapped block motion compensation (OBMC) are employed at the source decoder so that it can not only recover the lost macroblock more accurately, but also reduce blocking artifacts. Experimental results show that the proposed scheme can be an effective error protection scheme since proper video quality can be maintained under various channel bit error rates.