• The Journal of the Acoustical Society of Korea
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• v.20 no.6
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• pp.87-93
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• 2001

As a new type of a linear decorrelating receiver, the Pseudo-Decorrelator was presented for asynchronous code division multiple access systems by the author. In this paper, the concept of the Pseudo-Decorrelator is extended to derive a receiver for WCDMA uplink systems over an additive white Gaussian noise channel. Starting with the analysis of the multiple access components of the decision statistics, a non-square cross-correlation matrix for each bit is obtained. This cross-correlation matrix is then inverted, and the inverted matrix is applied to the decision statistics obtained from a conventional receiver. In this receiver, the detection process can be started after the first three consecutive bits are received. Simulation results are presented for K-user systems over an additive white Gaussian noise channel under the circumstances in which synchronization errors, including time delay errors and carrier phase errors exist. It is shown that the proposed receiver performs better than a conventional receiver and parallel interference canceller.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1844-1850
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• 2016

The bilateral filter can reduce the noise while preserving details computing the filtering output at each pixels as the average of neighboring pixels. In this paper, we propose a real-time system based on window division. Overall performance is increased due to the parallel architectures which computes five rows in the kernel window simultaneously but with pipelined scheduling. We consider the tradeoff between the filter performance and the hardware cost and the bit allocation has been determined by PSNR analysis. The proposed architecture is designed with verilogHDL and synthesized using Dongbu Hitek 110nm standard cell library. The proposed architecture shows 416Mpixels/s (397fps) of throughput at 416MHz of operating frequency with 132K gates.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.932-939
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• 1998

In this paper, we analyze the performance of a multicode-CDMA system which have been proposed for the multimedia communications. The performance of a multicode-CDMA system, providing good spectrum efficiency as well as serving various bit rates, is analyzed with multipath, frequency selective, slowly fading Rayleigh channel. Also the proposed scheme adopting RAKE receiver with MRC(Maximal Ratio Combine) is advantageous to multipath channel. For a practical channel modeling, the JTC(Joint Technical Committee) recommended channel model(JTC(AIR) 23-065R6) is applied to simulation. The proposed schemehas serial-to-parallel convertor which splits input data stream of 2 Mits/s into 20 branches o 100 kbits/s. From the result of simulation, the case of RAKE receiver with 3 fingers to reduce the system complexity required the relatively large $E_{b}/N_O$ of 0 dB~1.5 dB, compared to the case of RAKE receiver with the number of path finger to keep the average error rate to be $1{\times}10^{-3}$ in channel A.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7B
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• pp.686-694
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• 2002

In this paper, we introduce an improved sorting method of the IGIC(Improved initial stage Grouping Interference Canceller) system for advanced BER(Bit Error Rate) performance in DS-CDMA. Among non liner Interference Cancellers, the PIC(Parallel IC) with advanced initial stage by sorting method has the name of the IGIC(Improved initial stage Grouping Interference Canceller) system. In this system, All group are shared with the same number of users. But, if each group are divided the same users, so that difference of the signals strength appeared greatly in the same group. Up to this time, the weak signals have more effect of the MAI (Multiple Access Interference) from the strong signals in the same group. The proposed IC (Interference Canceller) to solve those problems has a better performance by using improved sorting method from IGIC system. A new sorting method is the technique that the strength of signals would be liked in the same group. So, the MAI is reduced as difference of signal strength minimize. Analysis of performance assayed to make comparison with other non liner interference canceller when power controlled and not one.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.4
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• pp.9-16
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• 2000

This paper shows the performance of a multiuser detection DS-CDMA receiver based on of the hybrid scheme of parallel interference cancellation (PIC) and successive interference cancellation (SIC). The proposed hybrid interference cancellation is presented and is compared with existing PIC, SIC and Hybrid It of other type schemes. The performance criteria used for comparison are complexity, delay and average bit error rate (BER) performance obtained by simulation in Rayleigh-fading channel (Jake's model) with additive white Gaussian noise (AWGN). In the proposed hybrid IC, the BER performance approximates the one of SIC and the delay is half of the SIC. And the number of cancellation of the hybrid It is reduced about a fourth.

• Journal of IKEEE
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• v.24 no.1
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• pp.225-231
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• 2020

In this paper, we propose a method to accelerate BWN based on FPGA with limited resources for embedded system. Because of the limited number of logic elements available, a single computing unit capable of handling Conv-layer, FC-layer of various sizes must be designed and reused. Also, if the input feature map can not be parallel processed at one time, the output must be calculated by reading the inputs several times. Since the number of available BRAM modules is limited, the number of data bits in the BWN accelerator must be minimized. The image classification processing time of the BWN accelerator is superior when compared with a embedded CPU and is faster than a desktop PC and 50% slower than a GPU system. Since the BWN accelerator uses a slow clock of 50MHz, it can be seen that the BWN accelerator is advantageous in performance versus power.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1493-1498
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• 2000

In this paper, we introduce a modified interference cancellation scheme to overcome MAI in DS-CDMA. Among ICs(Interference Cancellers), PIC(Parallel IC) requires the more complexity, and SIC(Successive IC) faces the problems of the long delay time. Most of all, the adaptive detector achieves the good BER performance using the adaptive filter conducted iteration algorithm. so it requires many iterations. To resolve the problems of them, we propose an improved adaptive detector that the received signal removed MAI through the sorting scheme and the cancellation method are fed into the adaptive filter. Because the improved input signal is fed into the adaptive filter, it has the same BER performance only using smaller iterations than the conventional adaptive detector, and the proposed detector having adaptive filter requires less complexity than the other detectors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.5C
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• pp.555-560
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• 2003

For synchronous direct sequence-code division multiple access (DS-CDMA) systems, the authors propose an adaptive radial basis function (RBF) receiver with suboptimal structure that reduces not only the complexity with regard to the number of centers but also the quantity of instructions required per one bit reception. The proposed receiver is constructed with parallel RBF networks. Each RBF network has the same procedure as the conventional RBF receiver. The performance of each RBF network is affected by interferences which are assigned to the other RBF networks because neither RBF network uses the full user set. To combat these interferences, the partial IC technique is employed. Monte Carlo simulations over additive white Gaussian noise (AWGN) channels confirm that the proposed receiver with its reduced complexity is able to obtain near-optimum performance. Moreover, the proposed receiver is able to properly cope with a various environment.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.3
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• pp.206-215
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• 2005

In this paper, we propose a new design method of Genetic Algorithm Processor(GAP) and Evolvable Hardware(EHW). All sorts of creature evolve its structure or shape in order to adapt itself to environments. Evolutionary Computation based on the process of natural selection not only searches the quasi-optimal solution through the evolution process, but also changes the structure to get best results. On the other hand, Genetic Algorithm(GA) is good fur finding solutions of complex optimization problems. However, it has a major drawback, which is its slow execution speed when is implemented in software of a conventional computer. Parallel processing has been one approach to overcome the speed problem of GA. In a point of view of GA, long bit string length caused the system of GA to spend much time that clear up the problem. Evolvable Hardware refers to the automation of electronic circuit design through artificial evolution, and is currently increased with the interested topic in a research domain and an engineering methodology. The studies of EHW generally use the XC6200 of Xilinx. The structure of XC6200 can configure with gate unit. Each unit has connected up, down, right and left cell. But the products can't use because had sterilized. So this paper uses Vertex-E (XCV2000E). The cell of FPGA is made up of Configuration Logic Block (CLB) and can't reconfigure with gate unit. This paper uses Vertex-E is composed of the component as cell of XC6200 cell in VertexE