• Proceedings of the KIEE Conference
• /
• 2005.05a
• /
• pp.144-147
• /
• 2005

This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.140-143
• /
• 2000

소형화와 안전성에서 보다 더 진보된 ECC( Elliptic Curve Cryptography) 암호화 알고리즘의 하드웨어적 구현을 제안한다. Basis는 VLSI 구현에 적합한 standard basis이며 m=193 ECC 승산기 회로를 설계하였다. Bit-Parallel 구조를 바탕으로 Digit-Serial/Bit-Parallel 방법으로 구현하였다. 제안된 구조는 VHDL 및 SYNOPSYS로 검증되었다.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.19 no.6
• /
• pp.3-15
• /
• 2009

Recently, Wu proposed a three small classes of finite fields $F_{2^n}$ for low-complexity bit-parallel multipliers. The proposed multipliers have low-complexities compared with those based on the irreducible pentanomials. In this paper, we propose a new Repeated Polynomial(RP) for low-complexity bit-parallel multipliers over $F_{2^n}$. Also, three classes of Irreducible Repeated polynomials are considered which are denoted, respectively, by case 1, case 2 and case3. The proposed RP bit-parallel multiplier has lower complexities than ones based on pentanomials. If we consider finite fields that have neither a ESP nor a trinomial as an irreducible polynomial when $n\leq1,000$. Then, in Wu''s result, only 11 finite fields exist for three types of irreducible polynomials when $n\leq1,000$. However, in our result, there are 181, 232, and 443 finite fields of case 1, 2 and 3, respectively.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.20 no.5
• /
• pp.11-22
• /
• 2010

Recently, Fan and Dai introduced a Shifted Polynomial Basis and construct a non-pipeline bit-parallel multiplier for $F_{2^n}$. As the name implies, the SPB is obtained by multiplying the polynomial basis 1, ${\alpha}$, ${\cdots}$, ${\alpha}^{n-1}$ by ${\alpha}^{-\upsilon}$. Therefore, it is easy to transform the elements PB and SPB representations. After, based on the Modified Shifted Polynomial Basis(MSPB), SPB bit-parallel Mastrovito type I and type II multipliers for all irreducible trinomials are presented. In this paper, we present a bit-parallel architecture to multiply in SPB. This multiplier have a space complexity efficient than all previously presented architecture when n ${\neq}$ 2k. The proposed multiplier has more efficient space complexity than the best-result when 1 ${\leq}$ k ${\leq}$ (n+1)/3. Also, when (n+2)/3 ${\leq}$ k < n/2 the proposed multiplier has more efficient space complexity than the best-result except for some cases.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.4 no.4
• /
• pp.278-285
• /
• 2011

This paper makes an analysis of the encoding structure and the decoding algorithm proposed by the DVB-S2 specification. The methods of implementing the LDPC decoder are fully serial decoder, the partially parallel decoder and the fully parallel decoder. The partial parallel scheme is the efficient selection to achieve appropriate trade-offs between hardware complexity and decoding speed. Therefore, this paper proposed an efficient memory structure for check node update block, bit node update block, and LLR memory.

• Journal of Convergence for Information Technology
• /
• v.11 no.8
• /
• pp.1-7
• /
• 2021

In this paper, a method of extending 1 bit by adding an external device to a parallel interface type Digital-to-Analog conversion(D/A C) circuit is presented. To do this, the principle of the D/A C circuit was examined, and the problems that occur when extending one bit by adding individual devices were analyzed, and a bit extension method of the D/A devices using an OP-Amp. circuit was presented. As the proposed method uses the high-precision characteristics of the OP-Amp., even if an error occurs in the device, only the overall size of the output waveform is affected, and the voltage reversal phenomenon that occurs between each bit does not occur. In order to confirm the effect of the proposed method, an experimental circuit was constructed and the absolute voltage of the output and the relative error were measured. As a result, a voltage error of 0.0756% appeared, confirming that the 0.195% requirement for one bit expansion by adding individual devices was sufficiently satisfied.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.11
• /
• pp.643-649
• /
• 2005

A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUD) sensors for precise MCG(MagnetoCardioGram) signal acquisitions. Such system needs to deal with hundreds of sensors, requiring fast signal sampling md precise analog-to-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit in 1 ks/s speed, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and specially designed parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 mili-second sampling interval. We extend the design into 256-channel hardware and analyze the speed .using the measured data from the 64-channel hardware. Since our design exploits full parallel processing, Assembly level coding, and NOP(No Operation) instruction for timing control, the design provides expandability and lowest system timing margin. Our result concludes that the data collection with 256-channel analog input signals can be done in 201.5us time-interval which is much shorter than the required 1 mili-second period.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.49 no.12
• /
• pp.683-689
• /
• 2000

Two-dimensional(2-D) fiber-optic code-division multiple-access(FO-CDMA) system utilizes the optical orthogonal signature pattern code(OOSPC) to encode and decode 2-D data. Encoded 2-D data are spatially multiplexed and transmitted through an image fiber and receiver recovers the intended data by means of thresholding process. OOSPC's construction methods based on expansion of the optical orthogonal code, which is used in one-dimensional(1-D) FO-CDMA system, are introduced. Each OOSPC's performances are compared by using the bit error rate(BER) of interfering OOSPC's of other users. From the results we verify that a balanced incomplete block design(BIBD) construction has the best performance among other mehtods. We also propose a decomposed bit-plane method for parallel transmission and recovery of 256 gray-scale images using OOSPC's constructed by the BIBD method. The simulation result encourages the feasibility of parallel transmission and recovery of multiuser's images.

• Journal of the Korea Society of Computer and Information
• /
• v.18 no.7
• /
• pp.1-10
• /
• 2013

In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2 instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD, ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07b
• /
• pp.902-905
• /
• 2004

A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUID) sensors for precision MCG signal acquisitions. Such system is composed of hundreds of sensors, requiring fast signal sampling and precise analog-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit 1ks/s, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 ms speed. The test result shows that the signal acquisition is done in 168 usuc which is much shorter than the required 1 ms period. This hardware will be extended to 256 channel data acquisition to be used for the diagnosis system.