• The Transactions of the Korea Information Processing Society
• /
• v.6 no.7
• /
• pp.1756-1769
• /
• 1999

Parallel paths in an interconnection network have some significance in that message transmission time can be reduced because message is divided into packets and transmitted in parallel through several paths, and also an whose nodes has 2n binary bit string, is an interconnection network which has a lower network cost than hypercube and its variation. In this paper, we analyze node disjoint parallel path in Folded Hyper-Star graph FHS(2n,n) proposed as the topology of parallel computers and, using the result, prove that the fault diameter of a Folded Hyper-Star graph FHS(2n,n) is 2n-1.

• ETRI Journal
• /
• v.32 no.2
• /
• pp.222-229
• /
• 2010

A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a $2{\times}2$ multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.10
• /
• pp.1-12
• /
• 1993

A multiprocessor system for high-speed processing of hybrid image coding algorithms such as H.261, MPEG, or Digital HDTV is presented in this study. Using a combination of highly parallel 32-bit microprocessor, DCT(Discrete Cosine Transform), and motion detection processor, a new processing module is designed for the implementation of high performance coding system. The sysyem is implemented to allow parallel processing since a single module alone cannot perform hybrid coding algorithms at high speed, and crossbar switch is used to realize various parallel processing architectures by altering interconnections between processing modules within the system.

• Proceedings of the IEEK Conference
• /
• 2000.09a
• /
• pp.951-954
• /
• 2000

In this paper, we present a multi-code parallel combinatory CDMA system using bi-orthogonal modulation to reduce envelope variation and improve bit error. .rate (BER) performance. In general, the dynamic range of the amplitude of the transmit signal is very large in the case of conventional multi-code CDMA systems, resulting in severe nonlinear distortion due to high power amplifier and thus significant BER performance degradation. The proposed system exhibits reduction of peak-to-average power ratio (PAPR) of the transmit signal amplitudes and significant performance improvement. We verify the performance of the proposed system by computer simulations under AWGN channel and flat fading channel.

• Proceedings of the KIEE Conference
• /
• 2003.11b
• /
• pp.79-82
• /
• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.864-867
• /
• 2005

In this paper we introduce a design of parallel architecture for wavelet transformation on FPGA. We implement wavelet transforms though lifting scheme and apply Daubechies4 transform equations. This technique has an advantage that we can obtain perfect reconstruction of the data. We divide our process to high pass filter and low pass filter. With this division, we can find coefficients from low and high pass filters simultaneously using parallel processing properties of FPGA to reduce processing time. From the equations, we have to design real number computation module, referred to IEEE754 standard. We choose 32 bit computation that is fine enough to reconstruct data. After that we arrange the real number module according to Daubechies4 transform though lifting scheme.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.62-65
• /
• 1998

This paper presents a method and implementation of the parallel distributed sample scrambler(DSS) in the cell-based ATM transmission environment. In the serial processing, it requires very high speed clock because the processing clock of the serial DSS is equal with the data transmission speed. In this paper, we develop a conversion method of the serial SRG(shift register generator) to 8bit parallel realization. In this case, it has a sample data processing problem which is a character of DSS. So, a theory of correction time movement is presented to solve this problem. We has developed a ASIC using this algorithm and verified the recommendation of ITU-T, I.432.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.4C
• /
• pp.370-378
• /
• 2007

The most appropriate low density parity check (LDPC) code for hybrid automatic repeat request (HARQ) system suitable for future multimedia communication systems is presented in this paper. HARQ system with punctured LDPC code is investigated at first. And two transmission schemes with parallel concatenated LDPC code are also presented and their performances are analyzed according to the various values of mean column weight (MCW). As a result, the parallel concatenated LDPC code with the diversity effect of information bit is considered to be more appropriate for HARQ system considering the throughput as well as error performance.

• Proceedings of the Korean Society of Medical Physics Conference
• /
• 2002.09a
• /
• pp.311-313
• /
• 2002

We are under development of a 3D PET scanner with depth of interaction (DOI) capable of high sensitivity and high resolution. In this scanner, a maximum data transfer rate of coincidence pair's event information is 10 Mcps and one event is a 64-bit data format. This maximum data transfer rate corresponds by 10 times a conventional PET scanner. A data acquisition system, which fulfills the specification of this scanner, is considered for parallel collection with banks including several coincidence units. Data transfer rate is improved by optimizing parameters of a message size, and so on.

• Journal of IKEEE
• /
• v.11 no.4
• /
• pp.198-204
• /
• 2007

For parallel and serially concatenated trellis coded modulation (TCM), improved iterative decoding schemes with a simple mechanism are proposed and their performances are compared with those of conventional decoding schemes. Simulation results have shown that the proposed schemes have provided a considerable decoding gain in additive white Gaussian noise (AWGN) channels and Rayleigh fading channels, even if they can be implemented by a simple modification of conventional decoding algorithms.